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Renamed port access function on RTLIL::Cell, added param access functions

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This commit is contained in:
Clifford Wolf 2014-07-31 16:38:54 +02:00
parent b5a9e51b96
commit cdae8abe16
46 changed files with 1086 additions and 1059 deletions
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170
passes/techmap/simplemap.cc
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@ -28,22 +28,22 @@ extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*,
static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->get("\\A");
RTLIL::SigSpec sig_y = cell->get("\\Y");
RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
for (int i = 0; i < SIZE(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
gate->set("\\A", sig_a[i]);
gate->set("\\Y", sig_y[i]);
gate->setPort("\\A", sig_a[i]);
gate->setPort("\\Y", sig_y[i]);
}
}
static void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->get("\\A");
RTLIL::SigSpec sig_y = cell->get("\\Y");
RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
@ -52,8 +52,8 @@ static void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
static void simplemap_bu0(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->get("\\A");
RTLIL::SigSpec sig_y = cell->get("\\Y");
RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
@ -62,9 +62,9 @@ static void simplemap_bu0(RTLIL::Module *module, RTLIL::Cell *cell)
static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->get("\\A");
RTLIL::SigSpec sig_b = cell->get("\\B");
RTLIL::SigSpec sig_y = cell->get("\\Y");
RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_b = cell->getPort("\\B");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
sig_b.extend_u0(SIZE(sig_y), cell->parameters.at("\\B_SIGNED").as_bool());
@ -75,8 +75,8 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
for (int i = 0; i < SIZE(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
gate->set("\\A", sig_t[i]);
gate->set("\\Y", sig_y[i]);
gate->setPort("\\A", sig_t[i]);
gate->setPort("\\Y", sig_y[i]);
}
sig_y = sig_t;
@ -91,16 +91,16 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
for (int i = 0; i < SIZE(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->set("\\A", sig_a[i]);
gate->set("\\B", sig_b[i]);
gate->set("\\Y", sig_y[i]);
gate->setPort("\\A", sig_a[i]);
gate->setPort("\\B", sig_b[i]);
gate->setPort("\\Y", sig_y[i]);
}
}
static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->get("\\A");
RTLIL::SigSpec sig_y = cell->get("\\Y");
RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
if (sig_y.size() == 0)
return;
@ -141,9 +141,9 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
}
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->set("\\A", sig_a[i]);
gate->set("\\B", sig_a[i+1]);
gate->set("\\Y", sig_t[i/2]);
gate->setPort("\\A", sig_a[i]);
gate->setPort("\\B", sig_a[i+1]);
gate->setPort("\\Y", sig_t[i/2]);
last_output_cell = gate;
}
@ -153,8 +153,8 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
if (cell->type == "$reduce_xnor") {
RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
gate->set("\\A", sig_a);
gate->set("\\Y", sig_t);
gate->setPort("\\A", sig_a);
gate->setPort("\\Y", sig_t);
last_output_cell = gate;
sig_a = sig_t;
}
@ -162,7 +162,7 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
if (last_output_cell == NULL) {
module->connect(RTLIL::SigSig(sig_y, sig_a));
} else {
last_output_cell->set("\\Y", sig_y);
last_output_cell->setPort("\\Y", sig_y);
}
}
@ -180,9 +180,9 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig)
}
RTLIL::Cell *gate = module->addCell(NEW_ID, "$_OR_");
gate->set("\\A", sig[i]);
gate->set("\\B", sig[i+1]);
gate->set("\\Y", sig_t[i/2]);
gate->setPort("\\A", sig[i]);
gate->setPort("\\B", sig[i+1]);
gate->setPort("\\Y", sig_t[i/2]);
}
sig = sig_t;
@ -194,10 +194,10 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig)
static void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->get("\\A");
RTLIL::SigSpec sig_a = cell->getPort("\\A");
logic_reduce(module, sig_a);
RTLIL::SigSpec sig_y = cell->get("\\Y");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
if (sig_y.size() == 0)
return;
@ -208,19 +208,19 @@ static void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
}
RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
gate->set("\\A", sig_a);
gate->set("\\Y", sig_y);
gate->setPort("\\A", sig_a);
gate->setPort("\\Y", sig_y);
}
static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->get("\\A");
RTLIL::SigSpec sig_a = cell->getPort("\\A");
logic_reduce(module, sig_a);
RTLIL::SigSpec sig_b = cell->get("\\B");
RTLIL::SigSpec sig_b = cell->getPort("\\B");
logic_reduce(module, sig_b);
RTLIL::SigSpec sig_y = cell->get("\\Y");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
if (sig_y.size() == 0)
return;
@ -236,39 +236,39 @@ static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
log_assert(!gate_type.empty());
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->set("\\A", sig_a);
gate->set("\\B", sig_b);
gate->set("\\Y", sig_y);
gate->setPort("\\A", sig_a);
gate->setPort("\\B", sig_b);
gate->setPort("\\Y", sig_y);
}
static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->get("\\A");
RTLIL::SigSpec sig_b = cell->get("\\B");
RTLIL::SigSpec sig_y = cell->get("\\Y");
RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_b = cell->getPort("\\B");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
for (int i = 0; i < SIZE(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, "$_MUX_");
gate->set("\\A", sig_a[i]);
gate->set("\\B", sig_b[i]);
gate->set("\\S", cell->get("\\S"));
gate->set("\\Y", sig_y[i]);
gate->setPort("\\A", sig_a[i]);
gate->setPort("\\B", sig_b[i]);
gate->setPort("\\S", cell->getPort("\\S"));
gate->setPort("\\Y", sig_y[i]);
}
}
static void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)
{
int offset = cell->parameters.at("\\OFFSET").as_int();
RTLIL::SigSpec sig_a = cell->get("\\A");
RTLIL::SigSpec sig_y = cell->get("\\Y");
RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
module->connect(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size())));
}
static void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_ab = cell->get("\\A");
sig_ab.append(cell->get("\\B"));
RTLIL::SigSpec sig_y = cell->get("\\Y");
RTLIL::SigSpec sig_ab = cell->getPort("\\A");
sig_ab.append(cell->getPort("\\B"));
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
module->connect(RTLIL::SigSig(sig_y, sig_ab));
}
@ -278,17 +278,17 @@ static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N';
char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
RTLIL::SigSpec sig_s = cell->get("\\SET");
RTLIL::SigSpec sig_r = cell->get("\\CLR");
RTLIL::SigSpec sig_q = cell->get("\\Q");
RTLIL::SigSpec sig_s = cell->getPort("\\SET");
RTLIL::SigSpec sig_r = cell->getPort("\\CLR");
RTLIL::SigSpec sig_q = cell->getPort("\\Q");
std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->set("\\S", sig_s[i]);
gate->set("\\R", sig_r[i]);
gate->set("\\Q", sig_q[i]);
gate->setPort("\\S", sig_s[i]);
gate->setPort("\\R", sig_r[i]);
gate->setPort("\\Q", sig_q[i]);
}
}
@ -297,17 +297,17 @@ static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell)
int width = cell->parameters.at("\\WIDTH").as_int();
char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
RTLIL::SigSpec sig_clk = cell->get("\\CLK");
RTLIL::SigSpec sig_d = cell->get("\\D");
RTLIL::SigSpec sig_q = cell->get("\\Q");
RTLIL::SigSpec sig_clk = cell->getPort("\\CLK");
RTLIL::SigSpec sig_d = cell->getPort("\\D");
RTLIL::SigSpec sig_q = cell->getPort("\\Q");
std::string gate_type = stringf("$_DFF_%c_", clk_pol);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->set("\\C", sig_clk);
gate->set("\\D", sig_d[i]);
gate->set("\\Q", sig_q[i]);
gate->setPort("\\C", sig_clk);
gate->setPort("\\D", sig_d[i]);
gate->setPort("\\Q", sig_q[i]);
}
}
@ -318,21 +318,21 @@ static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell)
char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N';
char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
RTLIL::SigSpec sig_clk = cell->get("\\CLK");
RTLIL::SigSpec sig_s = cell->get("\\SET");
RTLIL::SigSpec sig_r = cell->get("\\CLR");
RTLIL::SigSpec sig_d = cell->get("\\D");
RTLIL::SigSpec sig_q = cell->get("\\Q");
RTLIL::SigSpec sig_clk = cell->getPort("\\CLK");
RTLIL::SigSpec sig_s = cell->getPort("\\SET");
RTLIL::SigSpec sig_r = cell->getPort("\\CLR");
RTLIL::SigSpec sig_d = cell->getPort("\\D");
RTLIL::SigSpec sig_q = cell->getPort("\\Q");
std::string gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->set("\\C", sig_clk);
gate->set("\\S", sig_s[i]);
gate->set("\\R", sig_r[i]);
gate->set("\\D", sig_d[i]);
gate->set("\\Q", sig_q[i]);
gate->setPort("\\C", sig_clk);
gate->setPort("\\S", sig_s[i]);
gate->setPort("\\R", sig_r[i]);
gate->setPort("\\D", sig_d[i]);
gate->setPort("\\Q", sig_q[i]);
}
}
@ -346,20 +346,20 @@ static void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell)
while (int(rst_val.size()) < width)
rst_val.push_back(RTLIL::State::S0);
RTLIL::SigSpec sig_clk = cell->get("\\CLK");
RTLIL::SigSpec sig_rst = cell->get("\\ARST");
RTLIL::SigSpec sig_d = cell->get("\\D");
RTLIL::SigSpec sig_q = cell->get("\\Q");
RTLIL::SigSpec sig_clk = cell->getPort("\\CLK");
RTLIL::SigSpec sig_rst = cell->getPort("\\ARST");
RTLIL::SigSpec sig_d = cell->getPort("\\D");
RTLIL::SigSpec sig_q = cell->getPort("\\Q");
std::string gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol);
std::string gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0);
gate->set("\\C", sig_clk);
gate->set("\\R", sig_rst);
gate->set("\\D", sig_d[i]);
gate->set("\\Q", sig_q[i]);
gate->setPort("\\C", sig_clk);
gate->setPort("\\R", sig_rst);
gate->setPort("\\D", sig_d[i]);
gate->setPort("\\Q", sig_q[i]);
}
}
@ -368,17 +368,17 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
int width = cell->parameters.at("\\WIDTH").as_int();
char en_pol = cell->parameters.at("\\EN_POLARITY").as_bool() ? 'P' : 'N';
RTLIL::SigSpec sig_en = cell->get("\\EN");
RTLIL::SigSpec sig_d = cell->get("\\D");
RTLIL::SigSpec sig_q = cell->get("\\Q");
RTLIL::SigSpec sig_en = cell->getPort("\\EN");
RTLIL::SigSpec sig_d = cell->getPort("\\D");
RTLIL::SigSpec sig_q = cell->getPort("\\Q");
std::string gate_type = stringf("$_DLATCH_%c_", en_pol);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->set("\\E", sig_en);
gate->set("\\D", sig_d[i]);
gate->set("\\Q", sig_q[i]);
gate->setPort("\\E", sig_en);
gate->setPort("\\D", sig_d[i]);
gate->setPort("\\Q", sig_q[i]);
}
}