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Renamed port access function on RTLIL::Cell, added param access functions

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This commit is contained in:
Clifford Wolf 2014-07-31 16:38:54 +02:00
parent b5a9e51b96
commit cdae8abe16
46 changed files with 1086 additions and 1059 deletions
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48
passes/sat/expose.cc
View file

@ -83,8 +83,8 @@ static void find_dff_wires(std::set<std::string> &dff_wires, RTLIL::Module *modu
SigPool dffsignals;
for (auto &it : module->cells_) {
if (ct.cell_known(it.second->type) && it.second->has("\\Q"))
dffsignals.add(sigmap(it.second->get("\\Q")));
if (ct.cell_known(it.second->type) && it.second->hasPort("\\Q"))
dffsignals.add(sigmap(it.second->getPort("\\Q")));
}
for (auto &it : module->wires_) {
@ -113,10 +113,10 @@ static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL:
info.cell = it.second;
if (info.cell->type == "$dff") {
info.bit_clk = sigmap(info.cell->get("\\CLK")).to_single_sigbit();
info.bit_clk = sigmap(info.cell->getPort("\\CLK")).to_single_sigbit();
info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool();
std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->get("\\D")).to_sigbit_vector();
std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->get("\\Q")).to_sigbit_vector();
std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort("\\D")).to_sigbit_vector();
std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort("\\Q")).to_sigbit_vector();
for (size_t i = 0; i < sig_d.size(); i++) {
info.bit_d = sig_d.at(i);
bit_info[sig_q.at(i)] = info;
@ -125,12 +125,12 @@ static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL:
}
if (info.cell->type == "$adff") {
info.bit_clk = sigmap(info.cell->get("\\CLK")).to_single_sigbit();
info.bit_arst = sigmap(info.cell->get("\\ARST")).to_single_sigbit();
info.bit_clk = sigmap(info.cell->getPort("\\CLK")).to_single_sigbit();
info.bit_arst = sigmap(info.cell->getPort("\\ARST")).to_single_sigbit();
info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool();
info.arst_polarity = info.cell->parameters.at("\\ARST_POLARITY").as_bool();
std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->get("\\D")).to_sigbit_vector();
std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->get("\\Q")).to_sigbit_vector();
std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort("\\D")).to_sigbit_vector();
std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort("\\Q")).to_sigbit_vector();
std::vector<RTLIL::State> arst_value = info.cell->parameters.at("\\ARST_VALUE").bits;
for (size_t i = 0; i < sig_d.size(); i++) {
info.bit_d = sig_d.at(i);
@ -141,21 +141,21 @@ static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL:
}
if (info.cell->type == "$_DFF_N_" || info.cell->type == "$_DFF_P_") {
info.bit_clk = sigmap(info.cell->get("\\C")).to_single_sigbit();
info.bit_clk = sigmap(info.cell->getPort("\\C")).to_single_sigbit();
info.clk_polarity = info.cell->type == "$_DFF_P_";
info.bit_d = sigmap(info.cell->get("\\D")).to_single_sigbit();
bit_info[sigmap(info.cell->get("\\Q")).to_single_sigbit()] = info;
info.bit_d = sigmap(info.cell->getPort("\\D")).to_single_sigbit();
bit_info[sigmap(info.cell->getPort("\\Q")).to_single_sigbit()] = info;
continue;
}
if (info.cell->type.size() == 10 && info.cell->type.substr(0, 6) == "$_DFF_") {
info.bit_clk = sigmap(info.cell->get("\\C")).to_single_sigbit();
info.bit_arst = sigmap(info.cell->get("\\R")).to_single_sigbit();
info.bit_clk = sigmap(info.cell->getPort("\\C")).to_single_sigbit();
info.bit_arst = sigmap(info.cell->getPort("\\R")).to_single_sigbit();
info.clk_polarity = info.cell->type[6] == 'P';
info.arst_polarity = info.cell->type[7] == 'P';
info.arst_value = info.cell->type[0] == '1' ? RTLIL::State::S1 : RTLIL::State::S0;
info.bit_d = sigmap(info.cell->get("\\D")).to_single_sigbit();
bit_info[sigmap(info.cell->get("\\Q")).to_single_sigbit()] = info;
info.bit_d = sigmap(info.cell->getPort("\\D")).to_single_sigbit();
bit_info[sigmap(info.cell->getPort("\\Q")).to_single_sigbit()] = info;
continue;
}
}
@ -504,11 +504,11 @@ struct ExposePass : public Pass {
for (auto &cell_name : info.cells) {
RTLIL::Cell *cell = module->cells_.at(cell_name);
std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->get("\\Q")).to_sigbit_vector();
std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->getPort("\\Q")).to_sigbit_vector();
for (auto &bit : cell_q_bits)
if (wire_bits_set.count(bit))
bit = RTLIL::SigBit(wire_dummy_q, wire_dummy_q->width++);
cell->set("\\Q", cell_q_bits);
cell->setPort("\\Q", cell_q_bits);
}
RTLIL::Wire *wire_q = add_new_wire(module, wire->name + sep + "q", wire->width);
@ -540,8 +540,8 @@ struct ExposePass : public Pass {
c->parameters["\\A_SIGNED"] = 0;
c->parameters["\\A_WIDTH"] = 1;
c->parameters["\\Y_WIDTH"] = 1;
c->set("\\A", info.sig_clk);
c->set("\\Y", wire_c);
c->setPort("\\A", info.sig_clk);
c->setPort("\\Y", wire_c);
}
if (info.sig_arst != RTLIL::State::Sm)
@ -556,8 +556,8 @@ struct ExposePass : public Pass {
c->parameters["\\A_SIGNED"] = 0;
c->parameters["\\A_WIDTH"] = 1;
c->parameters["\\Y_WIDTH"] = 1;
c->set("\\A", info.sig_arst);
c->set("\\Y", wire_r);
c->setPort("\\A", info.sig_arst);
c->setPort("\\Y", wire_r);
}
RTLIL::Wire *wire_v = add_new_wire(module, wire->name + sep + "v", wire->width);
@ -602,8 +602,8 @@ struct ExposePass : public Pass {
log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
RTLIL::SigSpec sig;
if (cell->has(p->name))
sig = cell->get(p->name);
if (cell->hasPort(p->name))
sig = cell->getPort(p->name);
sig.extend(w->width);
if (w->port_input)
module->connect(RTLIL::SigSig(sig, w));

6
passes/sat/freduce.cc
View file

@ -624,7 +624,7 @@ struct FreduceWorker
bits_full_total += outputs.size();
}
if (inv_mode && it.second->type == "$_INV_")
inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->get("\\A")), sigmap(it.second->get("\\Y"))));
inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->getPort("\\A")), sigmap(it.second->getPort("\\Y"))));
}
int bits_count = 0;
@ -719,8 +719,8 @@ struct FreduceWorker
inv_sig = module->addWire(NEW_ID);
RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_INV_");
inv_cell->set("\\A", grp[0].bit);
inv_cell->set("\\Y", inv_sig);
inv_cell->setPort("\\A", grp[0].bit);
inv_cell->setPort("\\Y", inv_sig);
}
module->connect(RTLIL::SigSig(grp[i].bit, inv_sig));

56
passes/sat/miter.cc
View file

@ -129,8 +129,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
RTLIL::Wire *w2 = miter_module->addWire("\\in_" + RTLIL::unescape_id(w1->name), w1->width);
w2->port_input = true;
gold_cell->set(w1->name, w2);
gate_cell->set(w1->name, w2);
gold_cell->setPort(w1->name, w2);
gate_cell->setPort(w1->name, w2);
}
if (w1->port_output)
@ -141,8 +141,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
RTLIL::Wire *w2_gate = miter_module->addWire("\\gate_" + RTLIL::unescape_id(w1->name), w1->width);
w2_gate->port_output = flag_make_outputs;
gold_cell->set(w1->name, w2_gold);
gate_cell->set(w1->name, w2_gate);
gold_cell->setPort(w1->name, w2_gold);
gate_cell->setPort(w1->name, w2_gate);
RTLIL::SigSpec this_condition;
@ -156,9 +156,9 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
eqx_cell->parameters["\\Y_WIDTH"] = 1;
eqx_cell->parameters["\\A_SIGNED"] = 0;
eqx_cell->parameters["\\B_SIGNED"] = 0;
eqx_cell->set("\\A", RTLIL::SigSpec(w2_gold, i));
eqx_cell->set("\\B", RTLIL::State::Sx);
eqx_cell->set("\\Y", gold_x.extract(i, 1));
eqx_cell->setPort("\\A", RTLIL::SigSpec(w2_gold, i));
eqx_cell->setPort("\\B", RTLIL::State::Sx);
eqx_cell->setPort("\\Y", gold_x.extract(i, 1));
}
RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w2_gold->width);
@ -170,9 +170,9 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
or_gold_cell->parameters["\\Y_WIDTH"] = w2_gold->width;
or_gold_cell->parameters["\\A_SIGNED"] = 0;
or_gold_cell->parameters["\\B_SIGNED"] = 0;
or_gold_cell->set("\\A", w2_gold);
or_gold_cell->set("\\B", gold_x);
or_gold_cell->set("\\Y", gold_masked);
or_gold_cell->setPort("\\A", w2_gold);
or_gold_cell->setPort("\\B", gold_x);
or_gold_cell->setPort("\\Y", gold_masked);
RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, "$or");
or_gate_cell->parameters["\\A_WIDTH"] = w2_gate->width;
@ -180,9 +180,9 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
or_gate_cell->parameters["\\Y_WIDTH"] = w2_gate->width;
or_gate_cell->parameters["\\A_SIGNED"] = 0;
or_gate_cell->parameters["\\B_SIGNED"] = 0;
or_gate_cell->set("\\A", w2_gate);
or_gate_cell->set("\\B", gold_x);
or_gate_cell->set("\\Y", gate_masked);
or_gate_cell->setPort("\\A", w2_gate);
or_gate_cell->setPort("\\B", gold_x);
or_gate_cell->setPort("\\Y", gate_masked);
RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx");
eq_cell->parameters["\\A_WIDTH"] = w2_gold->width;
@ -190,10 +190,10 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
eq_cell->parameters["\\Y_WIDTH"] = 1;
eq_cell->parameters["\\A_SIGNED"] = 0;
eq_cell->parameters["\\B_SIGNED"] = 0;
eq_cell->set("\\A", gold_masked);
eq_cell->set("\\B", gate_masked);
eq_cell->set("\\Y", miter_module->addWire(NEW_ID));
this_condition = eq_cell->get("\\Y");
eq_cell->setPort("\\A", gold_masked);
eq_cell->setPort("\\B", gate_masked);
eq_cell->setPort("\\Y", miter_module->addWire(NEW_ID));
this_condition = eq_cell->getPort("\\Y");
}
else
{
@ -203,10 +203,10 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
eq_cell->parameters["\\Y_WIDTH"] = 1;
eq_cell->parameters["\\A_SIGNED"] = 0;
eq_cell->parameters["\\B_SIGNED"] = 0;
eq_cell->set("\\A", w2_gold);
eq_cell->set("\\B", w2_gate);
eq_cell->set("\\Y", miter_module->addWire(NEW_ID));
this_condition = eq_cell->get("\\Y");
eq_cell->setPort("\\A", w2_gold);
eq_cell->setPort("\\B", w2_gate);
eq_cell->setPort("\\Y", miter_module->addWire(NEW_ID));
this_condition = eq_cell->getPort("\\Y");
}
if (flag_make_outcmp)
@ -225,15 +225,15 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
reduce_cell->parameters["\\A_WIDTH"] = all_conditions.size();
reduce_cell->parameters["\\Y_WIDTH"] = 1;
reduce_cell->parameters["\\A_SIGNED"] = 0;
reduce_cell->set("\\A", all_conditions);
reduce_cell->set("\\Y", miter_module->addWire(NEW_ID));
all_conditions = reduce_cell->get("\\Y");
reduce_cell->setPort("\\A", all_conditions);
reduce_cell->setPort("\\Y", miter_module->addWire(NEW_ID));
all_conditions = reduce_cell->getPort("\\Y");
}
if (flag_make_assert) {
RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, "$assert");
assert_cell->set("\\A", all_conditions);
assert_cell->set("\\EN", RTLIL::SigSpec(1, 1));
assert_cell->setPort("\\A", all_conditions);
assert_cell->setPort("\\EN", RTLIL::SigSpec(1, 1));
}
RTLIL::Wire *w_trigger = miter_module->addWire("\\trigger");
@ -244,8 +244,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
not_cell->parameters["\\A_WIDTH"] = all_conditions.size();
not_cell->parameters["\\Y_WIDTH"] = w_trigger->width;
not_cell->parameters["\\A_SIGNED"] = 0;
not_cell->set("\\A", all_conditions);
not_cell->set("\\Y", w_trigger);
not_cell->setPort("\\A", all_conditions);
not_cell->setPort("\\Y", w_trigger);
miter_module->fixup_ports();

84
passes/sat/share.cc
View file

@ -77,7 +77,7 @@ struct ShareWorker
for (auto &pbit : portbits) {
if (pbit.cell->type == "$mux" || pbit.cell->type == "$pmux") {
std::set<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->get("\\S")).to_sigbit_set();
std::set<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->getPort("\\S")).to_sigbit_set();
terminal_bits.insert(bits.begin(), bits.end());
queue_bits.insert(bits.begin(), bits.end());
visited_cells.insert(pbit.cell);
@ -256,11 +256,11 @@ struct ShareWorker
if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool())
{
RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1;
if (unsigned_cell->get("\\A").to_sigbit_vector().back() != RTLIL::State::S0) {
if (unsigned_cell->getPort("\\A").to_sigbit_vector().back() != RTLIL::State::S0) {
unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1;
RTLIL::SigSpec new_a = unsigned_cell->get("\\A");
RTLIL::SigSpec new_a = unsigned_cell->getPort("\\A");
new_a.append_bit(RTLIL::State::S0);
unsigned_cell->set("\\A", new_a);
unsigned_cell->setPort("\\A", new_a);
}
unsigned_cell->parameters.at("\\A_SIGNED") = true;
unsigned_cell->check();
@ -269,17 +269,17 @@ struct ShareWorker
bool a_signed = c1->parameters.at("\\A_SIGNED").as_bool();
log_assert(a_signed == c2->parameters.at("\\A_SIGNED").as_bool());
RTLIL::SigSpec a1 = c1->get("\\A");
RTLIL::SigSpec y1 = c1->get("\\Y");
RTLIL::SigSpec a1 = c1->getPort("\\A");
RTLIL::SigSpec y1 = c1->getPort("\\Y");
RTLIL::SigSpec a2 = c2->get("\\A");
RTLIL::SigSpec y2 = c2->get("\\Y");
RTLIL::SigSpec a2 = c2->getPort("\\A");
RTLIL::SigSpec y2 = c2->getPort("\\Y");
int a_width = std::max(a1.size(), a2.size());
int y_width = std::max(y1.size(), y2.size());
if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->get("\\Y");
if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->get("\\Y");
if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->getPort("\\Y");
if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->getPort("\\Y");
RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act);
RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
@ -288,8 +288,8 @@ struct ShareWorker
supercell->parameters["\\A_SIGNED"] = a_signed;
supercell->parameters["\\A_WIDTH"] = a_width;
supercell->parameters["\\Y_WIDTH"] = y_width;
supercell->set("\\A", a);
supercell->set("\\Y", y);
supercell->setPort("\\A", a);
supercell->setPort("\\Y", y);
RTLIL::SigSpec new_y1(y, 0, y1.size());
RTLIL::SigSpec new_y2(y, 0, y2.size());
@ -314,9 +314,9 @@ struct ShareWorker
if (score_flipped < score_unflipped)
{
RTLIL::SigSpec tmp = c2->get("\\A");
c2->set("\\A", c2->get("\\B"));
c2->set("\\B", tmp);
RTLIL::SigSpec tmp = c2->getPort("\\A");
c2->setPort("\\A", c2->getPort("\\B"));
c2->setPort("\\B", tmp);
std::swap(c2->parameters.at("\\A_WIDTH"), c2->parameters.at("\\B_WIDTH"));
std::swap(c2->parameters.at("\\A_SIGNED"), c2->parameters.at("\\B_SIGNED"));
@ -328,11 +328,11 @@ struct ShareWorker
{
RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1;
if (unsigned_cell->get("\\A").to_sigbit_vector().back() != RTLIL::State::S0) {
if (unsigned_cell->getPort("\\A").to_sigbit_vector().back() != RTLIL::State::S0) {
unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1;
RTLIL::SigSpec new_a = unsigned_cell->get("\\A");
RTLIL::SigSpec new_a = unsigned_cell->getPort("\\A");
new_a.append_bit(RTLIL::State::S0);
unsigned_cell->set("\\A", new_a);
unsigned_cell->setPort("\\A", new_a);
}
unsigned_cell->parameters.at("\\A_SIGNED") = true;
modified_src_cells = true;
@ -341,11 +341,11 @@ struct ShareWorker
if (c1->parameters.at("\\B_SIGNED").as_bool() != c2->parameters.at("\\B_SIGNED").as_bool())
{
RTLIL::Cell *unsigned_cell = c1->parameters.at("\\B_SIGNED").as_bool() ? c2 : c1;
if (unsigned_cell->get("\\B").to_sigbit_vector().back() != RTLIL::State::S0) {
if (unsigned_cell->getPort("\\B").to_sigbit_vector().back() != RTLIL::State::S0) {
unsigned_cell->parameters.at("\\B_WIDTH") = unsigned_cell->parameters.at("\\B_WIDTH").as_int() + 1;
RTLIL::SigSpec new_b = unsigned_cell->get("\\B");
RTLIL::SigSpec new_b = unsigned_cell->getPort("\\B");
new_b.append_bit(RTLIL::State::S0);
unsigned_cell->set("\\B", new_b);
unsigned_cell->setPort("\\B", new_b);
}
unsigned_cell->parameters.at("\\B_SIGNED") = true;
modified_src_cells = true;
@ -365,13 +365,13 @@ struct ShareWorker
if (c1->type == "$shl" || c1->type == "$shr" || c1->type == "$sshl" || c1->type == "$sshr")
b_signed = false;
RTLIL::SigSpec a1 = c1->get("\\A");
RTLIL::SigSpec b1 = c1->get("\\B");
RTLIL::SigSpec y1 = c1->get("\\Y");
RTLIL::SigSpec a1 = c1->getPort("\\A");
RTLIL::SigSpec b1 = c1->getPort("\\B");
RTLIL::SigSpec y1 = c1->getPort("\\Y");
RTLIL::SigSpec a2 = c2->get("\\A");
RTLIL::SigSpec b2 = c2->get("\\B");
RTLIL::SigSpec y2 = c2->get("\\Y");
RTLIL::SigSpec a2 = c2->getPort("\\A");
RTLIL::SigSpec b2 = c2->getPort("\\B");
RTLIL::SigSpec y2 = c2->getPort("\\Y");
int a_width = std::max(a1.size(), a2.size());
int b_width = std::max(b1.size(), b2.size());
@ -381,20 +381,20 @@ struct ShareWorker
{
a_width = std::max(y_width, a_width);
if (a1.size() < y1.size()) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.size()), true)->get("\\Y");
if (a2.size() < y2.size()) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.size()), true)->get("\\Y");
if (a1.size() < y1.size()) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.size()), true)->getPort("\\Y");
if (a2.size() < y2.size()) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.size()), true)->getPort("\\Y");
if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->get("\\Y");
if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->get("\\Y");
if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->getPort("\\Y");
if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->getPort("\\Y");
}
else
{
if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->get("\\Y");
if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->get("\\Y");
if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->getPort("\\Y");
if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->getPort("\\Y");
}
if (b1.size() != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->get("\\Y");
if (b2.size() != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->get("\\Y");
if (b1.size() != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->getPort("\\Y");
if (b2.size() != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->getPort("\\Y");
RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act);
RTLIL::SigSpec b = module->Mux(NEW_ID, b2, b1, act);
@ -406,9 +406,9 @@ struct ShareWorker
supercell->parameters["\\A_WIDTH"] = a_width;
supercell->parameters["\\B_WIDTH"] = b_width;
supercell->parameters["\\Y_WIDTH"] = y_width;
supercell->set("\\A", a);
supercell->set("\\B", b);
supercell->set("\\Y", y);
supercell->setPort("\\A", a);
supercell->setPort("\\B", b);
supercell->setPort("\\Y", y);
supercell->check();
RTLIL::SigSpec new_y1(y, 0, y1.size());
@ -447,7 +447,7 @@ struct ShareWorker
for (auto &bit : pbits) {
if ((bit.cell->type == "$mux" || bit.cell->type == "$pmux") && bit.port == "\\S")
forbidden_controls_cache[cell].insert(bit.cell->get("\\S").extract(bit.offset, 1));
forbidden_controls_cache[cell].insert(bit.cell->getPort("\\S").extract(bit.offset, 1));
consumer_cells.insert(bit.cell);
}
@ -541,9 +541,9 @@ struct ShareWorker
std::set<int> used_in_b_parts;
int width = c->parameters.at("\\WIDTH").as_int();
std::vector<RTLIL::SigBit> sig_a = modwalker.sigmap(c->get("\\A"));
std::vector<RTLIL::SigBit> sig_b = modwalker.sigmap(c->get("\\B"));
std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->get("\\S"));
std::vector<RTLIL::SigBit> sig_a = modwalker.sigmap(c->getPort("\\A"));
std::vector<RTLIL::SigBit> sig_b = modwalker.sigmap(c->getPort("\\B"));
std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->getPort("\\S"));
for (auto &bit : sig_a)
if (cell_out_bits.count(bit))