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Renamed port access function on RTLIL::Cell, added param access functions

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This commit is contained in:
Clifford Wolf 2014-07-31 16:38:54 +02:00
parent b5a9e51b96
commit cdae8abe16
46 changed files with 1086 additions and 1059 deletions
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44
passes/proc/proc_arst.cc
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@ -35,45 +35,45 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp
for (auto cell : mod->cells())
{
if (cell->type == "$reduce_or" && cell->get("\\Y") == signal)
return check_signal(mod, cell->get("\\A"), ref, polarity);
if (cell->type == "$reduce_or" && cell->getPort("\\Y") == signal)
return check_signal(mod, cell->getPort("\\A"), ref, polarity);
if (cell->type == "$reduce_bool" && cell->get("\\Y") == signal)
return check_signal(mod, cell->get("\\A"), ref, polarity);
if (cell->type == "$reduce_bool" && cell->getPort("\\Y") == signal)
return check_signal(mod, cell->getPort("\\A"), ref, polarity);
if (cell->type == "$logic_not" && cell->get("\\Y") == signal) {
if (cell->type == "$logic_not" && cell->getPort("\\Y") == signal) {
polarity = !polarity;
return check_signal(mod, cell->get("\\A"), ref, polarity);
return check_signal(mod, cell->getPort("\\A"), ref, polarity);
}
if (cell->type == "$not" && cell->get("\\Y") == signal) {
if (cell->type == "$not" && cell->getPort("\\Y") == signal) {
polarity = !polarity;
return check_signal(mod, cell->get("\\A"), ref, polarity);
return check_signal(mod, cell->getPort("\\A"), ref, polarity);
}
if ((cell->type == "$eq" || cell->type == "$eqx") && cell->get("\\Y") == signal) {
if (cell->get("\\A").is_fully_const()) {
if (!cell->get("\\A").as_bool())
if ((cell->type == "$eq" || cell->type == "$eqx") && cell->getPort("\\Y") == signal) {
if (cell->getPort("\\A").is_fully_const()) {
if (!cell->getPort("\\A").as_bool())
polarity = !polarity;
return check_signal(mod, cell->get("\\B"), ref, polarity);
return check_signal(mod, cell->getPort("\\B"), ref, polarity);
}
if (cell->get("\\B").is_fully_const()) {
if (!cell->get("\\B").as_bool())
if (cell->getPort("\\B").is_fully_const()) {
if (!cell->getPort("\\B").as_bool())
polarity = !polarity;
return check_signal(mod, cell->get("\\A"), ref, polarity);
return check_signal(mod, cell->getPort("\\A"), ref, polarity);
}
}
if ((cell->type == "$ne" || cell->type == "$nex") && cell->get("\\Y") == signal) {
if (cell->get("\\A").is_fully_const()) {
if (cell->get("\\A").as_bool())
if ((cell->type == "$ne" || cell->type == "$nex") && cell->getPort("\\Y") == signal) {
if (cell->getPort("\\A").is_fully_const()) {
if (cell->getPort("\\A").as_bool())
polarity = !polarity;
return check_signal(mod, cell->get("\\B"), ref, polarity);
return check_signal(mod, cell->getPort("\\B"), ref, polarity);
}
if (cell->get("\\B").is_fully_const()) {
if (cell->get("\\B").as_bool())
if (cell->getPort("\\B").is_fully_const()) {
if (cell->getPort("\\B").as_bool())
polarity = !polarity;
return check_signal(mod, cell->get("\\A"), ref, polarity);
return check_signal(mod, cell->getPort("\\A"), ref, polarity);
}
}
}