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Renamed port access function on RTLIL::Cell, added param access functions

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This commit is contained in:
Clifford Wolf 2014-07-31 16:38:54 +02:00
parent b5a9e51b96
commit cdae8abe16
46 changed files with 1086 additions and 1059 deletions
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44
passes/proc/proc_arst.cc
View file

@ -35,45 +35,45 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp
for (auto cell : mod->cells())
{
if (cell->type == "$reduce_or" && cell->get("\\Y") == signal)
return check_signal(mod, cell->get("\\A"), ref, polarity);
if (cell->type == "$reduce_or" && cell->getPort("\\Y") == signal)
return check_signal(mod, cell->getPort("\\A"), ref, polarity);
if (cell->type == "$reduce_bool" && cell->get("\\Y") == signal)
return check_signal(mod, cell->get("\\A"), ref, polarity);
if (cell->type == "$reduce_bool" && cell->getPort("\\Y") == signal)
return check_signal(mod, cell->getPort("\\A"), ref, polarity);
if (cell->type == "$logic_not" && cell->get("\\Y") == signal) {
if (cell->type == "$logic_not" && cell->getPort("\\Y") == signal) {
polarity = !polarity;
return check_signal(mod, cell->get("\\A"), ref, polarity);
return check_signal(mod, cell->getPort("\\A"), ref, polarity);
}
if (cell->type == "$not" && cell->get("\\Y") == signal) {
if (cell->type == "$not" && cell->getPort("\\Y") == signal) {
polarity = !polarity;
return check_signal(mod, cell->get("\\A"), ref, polarity);
return check_signal(mod, cell->getPort("\\A"), ref, polarity);
}
if ((cell->type == "$eq" || cell->type == "$eqx") && cell->get("\\Y") == signal) {
if (cell->get("\\A").is_fully_const()) {
if (!cell->get("\\A").as_bool())
if ((cell->type == "$eq" || cell->type == "$eqx") && cell->getPort("\\Y") == signal) {
if (cell->getPort("\\A").is_fully_const()) {
if (!cell->getPort("\\A").as_bool())
polarity = !polarity;
return check_signal(mod, cell->get("\\B"), ref, polarity);
return check_signal(mod, cell->getPort("\\B"), ref, polarity);
}
if (cell->get("\\B").is_fully_const()) {
if (!cell->get("\\B").as_bool())
if (cell->getPort("\\B").is_fully_const()) {
if (!cell->getPort("\\B").as_bool())
polarity = !polarity;
return check_signal(mod, cell->get("\\A"), ref, polarity);
return check_signal(mod, cell->getPort("\\A"), ref, polarity);
}
}
if ((cell->type == "$ne" || cell->type == "$nex") && cell->get("\\Y") == signal) {
if (cell->get("\\A").is_fully_const()) {
if (cell->get("\\A").as_bool())
if ((cell->type == "$ne" || cell->type == "$nex") && cell->getPort("\\Y") == signal) {
if (cell->getPort("\\A").is_fully_const()) {
if (cell->getPort("\\A").as_bool())
polarity = !polarity;
return check_signal(mod, cell->get("\\B"), ref, polarity);
return check_signal(mod, cell->getPort("\\B"), ref, polarity);
}
if (cell->get("\\B").is_fully_const()) {
if (cell->get("\\B").as_bool())
if (cell->getPort("\\B").is_fully_const()) {
if (cell->getPort("\\B").as_bool())
polarity = !polarity;
return check_signal(mod, cell->get("\\A"), ref, polarity);
return check_signal(mod, cell->getPort("\\A"), ref, polarity);
}
}
}

88
passes/proc/proc_dff.cc
View file

@ -76,8 +76,8 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size());
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
cell->set("\\A", sync_low_signals);
cell->set("\\Y", sync_low_signals = mod->addWire(NEW_ID));
cell->setPort("\\A", sync_low_signals);
cell->setPort("\\Y", sync_low_signals = mod->addWire(NEW_ID));
}
if (sync_low_signals.size() > 0) {
@ -85,9 +85,9 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size());
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
cell->set("\\A", sync_low_signals);
cell->set("\\Y", mod->addWire(NEW_ID));
sync_high_signals.append(cell->get("\\Y"));
cell->setPort("\\A", sync_low_signals);
cell->setPort("\\Y", mod->addWire(NEW_ID));
sync_high_signals.append(cell->getPort("\\Y"));
}
if (sync_high_signals.size() > 1) {
@ -95,30 +95,30 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size());
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
cell->set("\\A", sync_high_signals);
cell->set("\\Y", sync_high_signals = mod->addWire(NEW_ID));
cell->setPort("\\A", sync_high_signals);
cell->setPort("\\Y", sync_high_signals = mod->addWire(NEW_ID));
}
RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, "$not");
inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size());
inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size());
inv_cell->set("\\A", sync_value);
inv_cell->set("\\Y", sync_value_inv = mod->addWire(NEW_ID, sig_d.size()));
inv_cell->setPort("\\A", sync_value);
inv_cell->setPort("\\Y", sync_value_inv = mod->addWire(NEW_ID, sig_d.size()));
RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, "$mux");
mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
mux_set_cell->set("\\A", sig_sr_set);
mux_set_cell->set("\\B", sync_value);
mux_set_cell->set("\\S", sync_high_signals);
mux_set_cell->set("\\Y", sig_sr_set = mod->addWire(NEW_ID, sig_d.size()));
mux_set_cell->setPort("\\A", sig_sr_set);
mux_set_cell->setPort("\\B", sync_value);
mux_set_cell->setPort("\\S", sync_high_signals);
mux_set_cell->setPort("\\Y", sig_sr_set = mod->addWire(NEW_ID, sig_d.size()));
RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, "$mux");
mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
mux_clr_cell->set("\\A", sig_sr_clr);
mux_clr_cell->set("\\B", sync_value_inv);
mux_clr_cell->set("\\S", sync_high_signals);
mux_clr_cell->set("\\Y", sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()));
mux_clr_cell->setPort("\\A", sig_sr_clr);
mux_clr_cell->setPort("\\B", sync_value_inv);
mux_clr_cell->setPort("\\S", sync_high_signals);
mux_clr_cell->setPort("\\Y", sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()));
}
std::stringstream sstr;
@ -130,11 +130,11 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1);
cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1);
cell->set("\\D", sig_d);
cell->set("\\Q", sig_q);
cell->set("\\CLK", clk);
cell->set("\\SET", sig_sr_set);
cell->set("\\CLR", sig_sr_clr);
cell->setPort("\\D", sig_d);
cell->setPort("\\Q", sig_q);
cell->setPort("\\CLK", clk);
cell->setPort("\\SET", sig_sr_set);
cell->setPort("\\CLR", sig_sr_clr);
log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",
cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
@ -154,22 +154,22 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec
inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0);
inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size());
inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size());
inv_set->set("\\A", sig_set);
inv_set->set("\\Y", sig_set_inv);
inv_set->setPort("\\A", sig_set);
inv_set->setPort("\\Y", sig_set_inv);
RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux");
mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
mux_sr_set->set(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size()));
mux_sr_set->set(set_polarity ? "\\B" : "\\A", sig_set);
mux_sr_set->set("\\Y", sig_sr_set);
mux_sr_set->set("\\S", set);
mux_sr_set->setPort(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size()));
mux_sr_set->setPort(set_polarity ? "\\B" : "\\A", sig_set);
mux_sr_set->setPort("\\Y", sig_sr_set);
mux_sr_set->setPort("\\S", set);
RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux");
mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
mux_sr_clr->set(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size()));
mux_sr_clr->set(set_polarity ? "\\B" : "\\A", sig_set_inv);
mux_sr_clr->set("\\Y", sig_sr_clr);
mux_sr_clr->set("\\S", set);
mux_sr_clr->setPort(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size()));
mux_sr_clr->setPort(set_polarity ? "\\B" : "\\A", sig_set_inv);
mux_sr_clr->setPort("\\Y", sig_sr_clr);
mux_sr_clr->setPort("\\S", set);
RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr");
cell->attributes = proc->attributes;
@ -177,11 +177,11 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec
cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1);
cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1);
cell->set("\\D", sig_in);
cell->set("\\Q", sig_out);
cell->set("\\CLK", clk);
cell->set("\\SET", sig_sr_set);
cell->set("\\CLR", sig_sr_clr);
cell->setPort("\\D", sig_in);
cell->setPort("\\Q", sig_out);
cell->setPort("\\CLK", clk);
cell->setPort("\\SET", sig_sr_set);
cell->setPort("\\CLR", sig_sr_clr);
log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(),
clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative");
@ -203,11 +203,11 @@ static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_
}
cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
cell->set("\\D", sig_in);
cell->set("\\Q", sig_out);
cell->setPort("\\D", sig_in);
cell->setPort("\\Q", sig_out);
if (arst)
cell->set("\\ARST", *arst);
cell->set("\\CLK", clk);
cell->setPort("\\ARST", *arst);
cell->setPort("\\CLK", clk);
log(" created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
if (arst)
@ -295,9 +295,9 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size());
cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size());
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
cell->set("\\A", inputs);
cell->set("\\B", compare);
cell->set("\\Y", sync_level->signal);
cell->setPort("\\A", inputs);
cell->setPort("\\B", compare);
cell->setPort("\\Y", sync_level->signal);
many_async_rules.clear();
}

30
passes/proc/proc_mux.cc
View file

@ -92,9 +92,9 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.size());
eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
eq_cell->set("\\A", sig);
eq_cell->set("\\B", comp);
eq_cell->set("\\Y", RTLIL::SigSpec(cmp_wire, cmp_wire->width++));
eq_cell->setPort("\\A", sig);
eq_cell->setPort("\\B", comp);
eq_cell->setPort("\\Y", RTLIL::SigSpec(cmp_wire, cmp_wire->width++));
}
}
@ -115,8 +115,8 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width);
any_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
any_cell->set("\\A", cmp_wire);
any_cell->set("\\Y", RTLIL::SigSpec(ctrl_wire));
any_cell->setPort("\\A", cmp_wire);
any_cell->setPort("\\Y", RTLIL::SigSpec(ctrl_wire));
}
return RTLIL::SigSpec(ctrl_wire);
@ -147,10 +147,10 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
mux_cell->attributes = sw->attributes;
mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size());
mux_cell->set("\\A", else_signal);
mux_cell->set("\\B", when_signal);
mux_cell->set("\\S", ctrl_sig);
mux_cell->set("\\Y", RTLIL::SigSpec(result_wire));
mux_cell->setPort("\\A", else_signal);
mux_cell->setPort("\\B", when_signal);
mux_cell->setPort("\\S", ctrl_sig);
mux_cell->setPort("\\Y", RTLIL::SigSpec(result_wire));
last_mux_cell = mux_cell;
return RTLIL::SigSpec(result_wire);
@ -159,21 +159,21 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw)
{
log_assert(last_mux_cell != NULL);
log_assert(when_signal.size() == last_mux_cell->get("\\A").size());
log_assert(when_signal.size() == last_mux_cell->getPort("\\A").size());
RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw);
log_assert(ctrl_sig.size() == 1);
last_mux_cell->type = "$pmux";
RTLIL::SigSpec new_s = last_mux_cell->get("\\S");
RTLIL::SigSpec new_s = last_mux_cell->getPort("\\S");
new_s.append(ctrl_sig);
last_mux_cell->set("\\S", new_s);
last_mux_cell->setPort("\\S", new_s);
RTLIL::SigSpec new_b = last_mux_cell->get("\\B");
RTLIL::SigSpec new_b = last_mux_cell->getPort("\\B");
new_b.append(when_signal);
last_mux_cell->set("\\B", new_b);
last_mux_cell->setPort("\\B", new_b);
last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->get("\\S").size();
last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->getPort("\\S").size();
}
static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval)