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Renamed port access function on RTLIL::Cell, added param access functions

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This commit is contained in:
Clifford Wolf 2014-07-31 16:38:54 +02:00
parent b5a9e51b96
commit cdae8abe16
46 changed files with 1086 additions and 1059 deletions
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196
passes/opt/opt_const.cc
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@ -73,7 +73,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
static void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val)
{
RTLIL::SigSpec Y = cell->get(out_port);
RTLIL::SigSpec Y = cell->getPort(out_port);
out_val.extend_u0(Y.size(), false);
log("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n",
@ -89,14 +89,14 @@ static void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell
static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, bool extend_u0, SigMap &sigmap)
{
std::string b_name = cell->has("\\B") ? "\\B" : "\\A";
std::string b_name = cell->hasPort("\\B") ? "\\B" : "\\A";
bool a_signed = cell->parameters.at("\\A_SIGNED").as_bool();
bool b_signed = cell->parameters.at(b_name + "_SIGNED").as_bool();
RTLIL::SigSpec sig_a = sigmap(cell->get("\\A"));
RTLIL::SigSpec sig_b = sigmap(cell->get(b_name));
RTLIL::SigSpec sig_y = sigmap(cell->get("\\Y"));
RTLIL::SigSpec sig_a = sigmap(cell->getPort("\\A"));
RTLIL::SigSpec sig_b = sigmap(cell->getPort(b_name));
RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y"));
if (extend_u0) {
sig_a.extend_u0(sig_y.size(), a_signed);
@ -161,17 +161,17 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com
RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
c->set("\\A", new_a);
c->setPort("\\A", new_a);
c->parameters["\\A_WIDTH"] = new_a.size();
c->parameters["\\A_SIGNED"] = false;
if (b_name == "\\B") {
c->set("\\B", new_b);
c->setPort("\\B", new_b);
c->parameters["\\B_WIDTH"] = new_b.size();
c->parameters["\\B_SIGNED"] = false;
}
c->set("\\Y", new_y);
c->setPort("\\Y", new_y);
c->parameters["\\Y_WIDTH"] = new_y->width;
c->check();
@ -210,8 +210,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
for (auto cell : module->cells())
if (design->selected(module, cell) && cell->type[0] == '$') {
if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") &&
cell->get("\\A").size() == 1 && cell->get("\\Y").size() == 1)
invert_map[assign_map(cell->get("\\Y"))] = assign_map(cell->get("\\A"));
cell->getPort("\\A").size() == 1 && cell->getPort("\\Y").size() == 1)
invert_map[assign_map(cell->getPort("\\Y"))] = assign_map(cell->getPort("\\A"));
if (ct_combinational.cell_known(cell->type))
for (auto &conn : cell->connections()) {
RTLIL::SigSpec sig = assign_map(conn.second);
@ -246,7 +246,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
if (cell->type == "$reduce_and")
{
RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
RTLIL::State new_a = RTLIL::State::S1;
for (auto &bit : sig_a.to_sigbit_vector())
@ -264,7 +264,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
cover("opt.opt_const.fine.$reduce_and");
log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
cell->set("\\A", sig_a = new_a);
cell->setPort("\\A", sig_a = new_a);
cell->parameters.at("\\A_WIDTH") = 1;
OPT_DID_SOMETHING = true;
did_something = true;
@ -273,7 +273,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
if (cell->type == "$logic_not" || cell->type == "$logic_and" || cell->type == "$logic_or" || cell->type == "$reduce_or" || cell->type == "$reduce_bool")
{
RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
RTLIL::State new_a = RTLIL::State::S0;
for (auto &bit : sig_a.to_sigbit_vector())
@ -291,7 +291,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
cover_list("opt.opt_const.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type);
log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
cell->set("\\A", sig_a = new_a);
cell->setPort("\\A", sig_a = new_a);
cell->parameters.at("\\A_WIDTH") = 1;
OPT_DID_SOMETHING = true;
did_something = true;
@ -300,7 +300,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
if (cell->type == "$logic_and" || cell->type == "$logic_or")
{
RTLIL::SigSpec sig_b = assign_map(cell->get("\\B"));
RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
RTLIL::State new_b = RTLIL::State::S0;
for (auto &bit : sig_b.to_sigbit_vector())
@ -318,7 +318,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
cover_list("opt.opt_const.fine.B", "$logic_and", "$logic_or", cell->type);
log("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b));
cell->set("\\B", sig_b = new_b);
cell->setPort("\\B", sig_b = new_b);
cell->parameters.at("\\B_WIDTH") = 1;
OPT_DID_SOMETHING = true;
did_something = true;
@ -326,13 +326,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
}
}
if (cell->type == "$logic_or" && (assign_map(cell->get("\\A")) == RTLIL::State::S1 || assign_map(cell->get("\\B")) == RTLIL::State::S1)) {
if (cell->type == "$logic_or" && (assign_map(cell->getPort("\\A")) == RTLIL::State::S1 || assign_map(cell->getPort("\\B")) == RTLIL::State::S1)) {
cover("opt.opt_const.one_high");
replace_cell(assign_map, module, cell, "one high", "\\Y", RTLIL::State::S1);
goto next_cell;
}
if (cell->type == "$logic_and" && (assign_map(cell->get("\\A")) == RTLIL::State::S0 || assign_map(cell->get("\\B")) == RTLIL::State::S0)) {
if (cell->type == "$logic_and" && (assign_map(cell->getPort("\\A")) == RTLIL::State::S0 || assign_map(cell->getPort("\\B")) == RTLIL::State::S0)) {
cover("opt.opt_const.one_low");
replace_cell(assign_map, module, cell, "one low", "\\Y", RTLIL::State::S0);
goto next_cell;
@ -344,8 +344,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
cell->type == "$neg" || cell->type == "$add" || cell->type == "$sub" ||
cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || cell->type == "$pow")
{
RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
RTLIL::SigSpec sig_b = cell->has("\\B") ? assign_map(cell->get("\\B")) : RTLIL::SigSpec();
RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
RTLIL::SigSpec sig_b = cell->hasPort("\\B") ? assign_map(cell->getPort("\\B")) : RTLIL::SigSpec();
if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" || cell->type == "$shift" || cell->type == "$shiftx")
sig_a = RTLIL::SigSpec();
@ -366,31 +366,31 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt")
replace_cell(assign_map, module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx);
else
replace_cell(assign_map, module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->get("\\Y").size()));
replace_cell(assign_map, module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->getPort("\\Y").size()));
goto next_cell;
}
}
if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->get("\\Y").size() == 1 &&
invert_map.count(assign_map(cell->get("\\A"))) != 0) {
if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->getPort("\\Y").size() == 1 &&
invert_map.count(assign_map(cell->getPort("\\A"))) != 0) {
cover_list("opt.opt_const.invert.double", "$_INV_", "$not", "$logic_not", cell->type);
replace_cell(assign_map, module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->get("\\A"))));
replace_cell(assign_map, module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->getPort("\\A"))));
goto next_cell;
}
if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->get("\\S"))) != 0) {
if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->getPort("\\S"))) != 0) {
cover_list("opt.opt_const.invert.muxsel", "$_MUX_", "$mux", cell->type);
RTLIL::SigSpec tmp = cell->get("\\A");
cell->set("\\A", cell->get("\\B"));
cell->set("\\B", tmp);
cell->set("\\S", invert_map.at(assign_map(cell->get("\\S"))));
RTLIL::SigSpec tmp = cell->getPort("\\A");
cell->setPort("\\A", cell->getPort("\\B"));
cell->setPort("\\B", tmp);
cell->setPort("\\S", invert_map.at(assign_map(cell->getPort("\\S"))));
OPT_DID_SOMETHING = true;
did_something = true;
goto next_cell;
}
if (cell->type == "$_INV_") {
RTLIL::SigSpec input = cell->get("\\A");
RTLIL::SigSpec input = cell->getPort("\\A");
assign_map.apply(input);
if (input.match("1")) ACTION_DO_Y(0);
if (input.match("0")) ACTION_DO_Y(1);
@ -399,8 +399,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
if (cell->type == "$_AND_") {
RTLIL::SigSpec input;
input.append(cell->get("\\B"));
input.append(cell->get("\\A"));
input.append(cell->getPort("\\B"));
input.append(cell->getPort("\\A"));
assign_map.apply(input);
if (input.match(" 0")) ACTION_DO_Y(0);
if (input.match("0 ")) ACTION_DO_Y(0);
@ -418,8 +418,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
if (cell->type == "$_OR_") {
RTLIL::SigSpec input;
input.append(cell->get("\\B"));
input.append(cell->get("\\A"));
input.append(cell->getPort("\\B"));
input.append(cell->getPort("\\A"));
assign_map.apply(input);
if (input.match(" 1")) ACTION_DO_Y(1);
if (input.match("1 ")) ACTION_DO_Y(1);
@ -437,8 +437,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
if (cell->type == "$_XOR_") {
RTLIL::SigSpec input;
input.append(cell->get("\\B"));
input.append(cell->get("\\A"));
input.append(cell->getPort("\\B"));
input.append(cell->getPort("\\A"));
assign_map.apply(input);
if (input.match("00")) ACTION_DO_Y(0);
if (input.match("01")) ACTION_DO_Y(1);
@ -452,9 +452,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
if (cell->type == "$_MUX_") {
RTLIL::SigSpec input;
input.append(cell->get("\\S"));
input.append(cell->get("\\B"));
input.append(cell->get("\\A"));
input.append(cell->getPort("\\S"));
input.append(cell->getPort("\\B"));
input.append(cell->getPort("\\A"));
assign_map.apply(input);
if (input.extract(2, 1) == input.extract(1, 1))
ACTION_DO("\\Y", input.extract(2, 1));
@ -464,9 +464,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
if (input.match("10 ")) {
cover("opt.opt_const.mux_to_inv");
cell->type = "$_INV_";
cell->set("\\A", input.extract(0, 1));
cell->unset("\\B");
cell->unset("\\S");
cell->setPort("\\A", input.extract(0, 1));
cell->unsetPort("\\B");
cell->unsetPort("\\S");
goto next_cell;
}
if (input.match("11 ")) ACTION_DO_Y(1);
@ -483,8 +483,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
if (cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex")
{
RTLIL::SigSpec a = cell->get("\\A");
RTLIL::SigSpec b = cell->get("\\B");
RTLIL::SigSpec a = cell->getPort("\\A");
RTLIL::SigSpec b = cell->getPort("\\B");
if (cell->parameters["\\A_WIDTH"].as_int() != cell->parameters["\\B_WIDTH"].as_int()) {
int width = std::max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int());
@ -519,8 +519,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
if (new_a.size() < a.size() || new_b.size() < b.size()) {
cover_list("opt.opt_const.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type);
cell->set("\\A", new_a);
cell->set("\\B", new_b);
cell->setPort("\\A", new_a);
cell->setPort("\\B", new_b);
cell->parameters["\\A_WIDTH"] = new_a.size();
cell->parameters["\\B_WIDTH"] = new_b.size();
}
@ -529,26 +529,26 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
if ((cell->type == "$eq" || cell->type == "$ne") && cell->parameters["\\Y_WIDTH"].as_int() == 1 &&
cell->parameters["\\A_WIDTH"].as_int() == 1 && cell->parameters["\\B_WIDTH"].as_int() == 1)
{
RTLIL::SigSpec a = assign_map(cell->get("\\A"));
RTLIL::SigSpec b = assign_map(cell->get("\\B"));
RTLIL::SigSpec a = assign_map(cell->getPort("\\A"));
RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
if (a.is_fully_const()) {
cover_list("opt.opt_const.eqneq.swapconst", "$eq", "$ne", cell->type);
RTLIL::SigSpec tmp = cell->get("\\A");
cell->set("\\A", cell->get("\\B"));
cell->set("\\B", tmp);
RTLIL::SigSpec tmp = cell->getPort("\\A");
cell->setPort("\\A", cell->getPort("\\B"));
cell->setPort("\\B", tmp);
}
if (b.is_fully_const()) {
if (b.as_bool() == (cell->type == "$eq")) {
RTLIL::SigSpec input = b;
ACTION_DO("\\Y", cell->get("\\A"));
ACTION_DO("\\Y", cell->getPort("\\A"));
} else {
cover_list("opt.opt_const.eqneq.isnot", "$eq", "$ne", cell->type);
cell->type = "$not";
cell->parameters.erase("\\B_WIDTH");
cell->parameters.erase("\\B_SIGNED");
cell->unset("\\B");
cell->unsetPort("\\B");
}
goto next_cell;
}
@ -562,8 +562,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
if (cell->type == "$add" || cell->type == "$sub" || cell->type == "$or" || cell->type == "$xor")
{
RTLIL::SigSpec a = assign_map(cell->get("\\A"));
RTLIL::SigSpec b = assign_map(cell->get("\\B"));
RTLIL::SigSpec a = assign_map(cell->getPort("\\A"));
RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
if (cell->type != "$sub" && a.is_fully_const() && a.as_bool() == false)
identity_wrt_b = true;
@ -574,7 +574,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" || cell->type == "$shift" || cell->type == "$shiftx")
{
RTLIL::SigSpec b = assign_map(cell->get("\\B"));
RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
if (b.is_fully_const() && b.as_bool() == false)
identity_wrt_a = true, identity_bu0 = true;
@ -582,8 +582,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
if (cell->type == "$mul")
{
RTLIL::SigSpec a = assign_map(cell->get("\\A"));
RTLIL::SigSpec b = assign_map(cell->get("\\B"));
RTLIL::SigSpec a = assign_map(cell->getPort("\\A"));
RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
if (a.is_fully_const() && a.size() <= 32 && a.as_int() == 1)
identity_wrt_b = true;
@ -594,7 +594,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
if (cell->type == "$div")
{
RTLIL::SigSpec b = assign_map(cell->get("\\B"));
RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
if (b.is_fully_const() && b.size() <= 32 && b.as_int() == 1)
identity_wrt_a = true;
@ -611,13 +611,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B');
if (!identity_wrt_a) {
cell->set("\\A", cell->get("\\B"));
cell->setPort("\\A", cell->getPort("\\B"));
cell->parameters.at("\\A_WIDTH") = cell->parameters.at("\\B_WIDTH");
cell->parameters.at("\\A_SIGNED") = cell->parameters.at("\\B_SIGNED");
}
cell->type = identity_bu0 ? "$bu0" : "$pos";
cell->unset("\\B");
cell->unsetPort("\\B");
cell->parameters.erase("\\B_WIDTH");
cell->parameters.erase("\\B_SIGNED");
cell->check();
@ -629,18 +629,18 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
}
if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") &&
cell->get("\\A") == RTLIL::SigSpec(0, 1) && cell->get("\\B") == RTLIL::SigSpec(1, 1)) {
cell->getPort("\\A") == RTLIL::SigSpec(0, 1) && cell->getPort("\\B") == RTLIL::SigSpec(1, 1)) {
cover_list("opt.opt_const.mux_bool", "$mux", "$_MUX_", cell->type);
replace_cell(assign_map, module, cell, "mux_bool", "\\Y", cell->get("\\S"));
replace_cell(assign_map, module, cell, "mux_bool", "\\Y", cell->getPort("\\S"));
goto next_cell;
}
if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") &&
cell->get("\\A") == RTLIL::SigSpec(1, 1) && cell->get("\\B") == RTLIL::SigSpec(0, 1)) {
cell->getPort("\\A") == RTLIL::SigSpec(1, 1) && cell->getPort("\\B") == RTLIL::SigSpec(0, 1)) {
cover_list("opt.opt_const.mux_invert", "$mux", "$_MUX_", cell->type);
cell->set("\\A", cell->get("\\S"));
cell->unset("\\B");
cell->unset("\\S");
cell->setPort("\\A", cell->getPort("\\S"));
cell->unsetPort("\\B");
cell->unsetPort("\\S");
if (cell->type == "$mux") {
cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"];
@ -654,10 +654,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
goto next_cell;
}
if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->get("\\A") == RTLIL::SigSpec(0, 1)) {
if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\A") == RTLIL::SigSpec(0, 1)) {
cover_list("opt.opt_const.mux_and", "$mux", "$_MUX_", cell->type);
cell->set("\\A", cell->get("\\S"));
cell->unset("\\S");
cell->setPort("\\A", cell->getPort("\\S"));
cell->unsetPort("\\S");
if (cell->type == "$mux") {
cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"];
@ -673,10 +673,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
goto next_cell;
}
if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->get("\\B") == RTLIL::SigSpec(1, 1)) {
if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\B") == RTLIL::SigSpec(1, 1)) {
cover_list("opt.opt_const.mux_or", "$mux", "$_MUX_", cell->type);
cell->set("\\B", cell->get("\\S"));
cell->unset("\\S");
cell->setPort("\\B", cell->getPort("\\S"));
cell->unsetPort("\\S");
if (cell->type == "$mux") {
cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"];
@ -694,22 +694,22 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
if (mux_undef && (cell->type == "$mux" || cell->type == "$pmux")) {
RTLIL::SigSpec new_a, new_b, new_s;
int width = cell->get("\\A").size();
if ((cell->get("\\A").is_fully_undef() && cell->get("\\B").is_fully_undef()) ||
cell->get("\\S").is_fully_undef()) {
int width = cell->getPort("\\A").size();
if ((cell->getPort("\\A").is_fully_undef() && cell->getPort("\\B").is_fully_undef()) ||
cell->getPort("\\S").is_fully_undef()) {
cover_list("opt.opt_const.mux_undef", "$mux", "$pmux", cell->type);
replace_cell(assign_map, module, cell, "mux_undef", "\\Y", cell->get("\\A"));
replace_cell(assign_map, module, cell, "mux_undef", "\\Y", cell->getPort("\\A"));
goto next_cell;
}
for (int i = 0; i < cell->get("\\S").size(); i++) {
RTLIL::SigSpec old_b = cell->get("\\B").extract(i*width, width);
RTLIL::SigSpec old_s = cell->get("\\S").extract(i, 1);
for (int i = 0; i < cell->getPort("\\S").size(); i++) {
RTLIL::SigSpec old_b = cell->getPort("\\B").extract(i*width, width);
RTLIL::SigSpec old_s = cell->getPort("\\S").extract(i, 1);
if (old_b.is_fully_undef() || old_s.is_fully_undef())
continue;
new_b.append(old_b);
new_s.append(old_s);
}
new_a = cell->get("\\A");
new_a = cell->getPort("\\A");
if (new_a.is_fully_undef() && new_s.size() > 0) {
new_a = new_b.extract((new_s.size()-1)*width, width);
new_b = new_b.extract(0, (new_s.size()-1)*width);
@ -725,11 +725,11 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
replace_cell(assign_map, module, cell, "mux_sel01", "\\Y", new_s);
goto next_cell;
}
if (cell->get("\\S").size() != new_s.size()) {
if (cell->getPort("\\S").size() != new_s.size()) {
cover_list("opt.opt_const.mux_reduce", "$mux", "$pmux", cell->type);
cell->set("\\A", new_a);
cell->set("\\B", new_b);
cell->set("\\S", new_s);
cell->setPort("\\A", new_a);
cell->setPort("\\B", new_b);
cell->setPort("\\S", new_s);
if (new_s.size() > 1) {
cell->type = "$pmux";
cell->parameters["\\S_WIDTH"] = new_s.size();
@ -744,7 +744,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
#define FOLD_1ARG_CELL(_t) \
if (cell->type == "$" #_t) { \
RTLIL::SigSpec a = cell->get("\\A"); \
RTLIL::SigSpec a = cell->getPort("\\A"); \
assign_map.apply(a); \
if (a.is_fully_const()) { \
RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \
@ -758,8 +758,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
}
#define FOLD_2ARG_CELL(_t) \
if (cell->type == "$" #_t) { \
RTLIL::SigSpec a = cell->get("\\A"); \
RTLIL::SigSpec b = cell->get("\\B"); \
RTLIL::SigSpec a = cell->getPort("\\A"); \
RTLIL::SigSpec b = cell->getPort("\\B"); \
assign_map.apply(a), assign_map.apply(b); \
if (a.is_fully_const() && b.is_fully_const()) { \
RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const(), \
@ -815,13 +815,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
// be very conservative with optimizing $mux cells as we do not want to break mux trees
if (cell->type == "$mux") {
RTLIL::SigSpec input = assign_map(cell->get("\\S"));
RTLIL::SigSpec inA = assign_map(cell->get("\\A"));
RTLIL::SigSpec inB = assign_map(cell->get("\\B"));
RTLIL::SigSpec input = assign_map(cell->getPort("\\S"));
RTLIL::SigSpec inA = assign_map(cell->getPort("\\A"));
RTLIL::SigSpec inB = assign_map(cell->getPort("\\B"));
if (input.is_fully_const())
ACTION_DO("\\Y", input.as_bool() ? cell->get("\\B") : cell->get("\\A"));
ACTION_DO("\\Y", input.as_bool() ? cell->getPort("\\B") : cell->getPort("\\A"));
else if (inA == inB)
ACTION_DO("\\Y", cell->get("\\A"));
ACTION_DO("\\Y", cell->getPort("\\A"));
}
if (!keepdc && cell->type == "$mul")
@ -830,9 +830,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
bool b_signed = cell->parameters["\\B_SIGNED"].as_bool();
bool swapped_ab = false;
RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
RTLIL::SigSpec sig_b = assign_map(cell->get("\\B"));
RTLIL::SigSpec sig_y = assign_map(cell->get("\\Y"));
RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y"));
if (sig_b.is_fully_const() && sig_b.size() <= 32)
std::swap(sig_a, sig_b), std::swap(a_signed, b_signed), swapped_ab = true;
@ -868,7 +868,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
a_val, cell->name.c_str(), module->name.c_str(), i);
if (!swapped_ab) {
cell->set("\\A", cell->get("\\B"));
cell->setPort("\\A", cell->getPort("\\B"));
cell->parameters["\\A_WIDTH"] = cell->parameters["\\B_WIDTH"];
cell->parameters["\\A_SIGNED"] = cell->parameters["\\B_SIGNED"];
}
@ -881,7 +881,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
cell->type = "$shl";
cell->parameters["\\B_WIDTH"] = SIZE(new_b);
cell->parameters["\\B_SIGNED"] = false;
cell->set("\\B", new_b);
cell->setPort("\\B", new_b);
cell->check();
OPT_DID_SOMETHING = true;

22
passes/opt/opt_muxtree.cc
View file

@ -86,10 +86,10 @@ struct OptMuxtreeWorker
{
if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux")
{
RTLIL::SigSpec sig_a = cell->get("\\A");
RTLIL::SigSpec sig_b = cell->get("\\B");
RTLIL::SigSpec sig_s = cell->get("\\S");
RTLIL::SigSpec sig_y = cell->get("\\Y");
RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_b = cell->getPort("\\B");
RTLIL::SigSpec sig_s = cell->getPort("\\S");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
muxinfo_t muxinfo;
muxinfo.cell = cell;
@ -192,10 +192,10 @@ struct OptMuxtreeWorker
continue;
}
RTLIL::SigSpec sig_a = mi.cell->get("\\A");
RTLIL::SigSpec sig_b = mi.cell->get("\\B");
RTLIL::SigSpec sig_s = mi.cell->get("\\S");
RTLIL::SigSpec sig_y = mi.cell->get("\\Y");
RTLIL::SigSpec sig_a = mi.cell->getPort("\\A");
RTLIL::SigSpec sig_b = mi.cell->getPort("\\B");
RTLIL::SigSpec sig_s = mi.cell->getPort("\\S");
RTLIL::SigSpec sig_y = mi.cell->getPort("\\Y");
RTLIL::SigSpec sig_ports = sig_b;
sig_ports.append(sig_a);
@ -220,9 +220,9 @@ struct OptMuxtreeWorker
}
}
mi.cell->set("\\A", new_sig_a);
mi.cell->set("\\B", new_sig_b);
mi.cell->set("\\S", new_sig_s);
mi.cell->setPort("\\A", new_sig_a);
mi.cell->setPort("\\B", new_sig_b);
mi.cell->setPort("\\S", new_sig_s);
if (new_sig_s.size() == 1) {
mi.cell->type = "$mux";
mi.cell->parameters.erase("\\S_WIDTH");

80
passes/opt/opt_reduce.cc
View file

@ -42,7 +42,7 @@ struct OptReduceWorker
return;
cells.erase(cell);
RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
std::set<RTLIL::SigBit> new_sig_a_bits;
for (auto &bit : sig_a.to_sigbit_set())
@ -72,8 +72,8 @@ struct OptReduceWorker
for (auto child_cell : drivers.find(bit)) {
if (child_cell->type == cell->type) {
opt_reduce(cells, drivers, child_cell);
if (child_cell->get("\\Y")[0] == bit) {
std::set<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->get("\\A")).to_sigbit_set();
if (child_cell->getPort("\\Y")[0] == bit) {
std::set<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->getPort("\\A")).to_sigbit_set();
new_sig_a_bits.insert(child_sig_a_bits.begin(), child_sig_a_bits.end());
} else
new_sig_a_bits.insert(RTLIL::State::S0);
@ -86,23 +86,23 @@ struct OptReduceWorker
RTLIL::SigSpec new_sig_a(new_sig_a_bits);
if (new_sig_a != sig_a || sig_a.size() != cell->get("\\A").size()) {
if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) {
log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
did_something = true;
OPT_DID_SOMETHING = true;
total_count++;
}
cell->set("\\A", new_sig_a);
cell->setPort("\\A", new_sig_a);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(new_sig_a.size());
return;
}
void opt_mux(RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
RTLIL::SigSpec sig_b = assign_map(cell->get("\\B"));
RTLIL::SigSpec sig_s = assign_map(cell->get("\\S"));
RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
RTLIL::SigSpec sig_s = assign_map(cell->getPort("\\S"));
RTLIL::SigSpec new_sig_b, new_sig_s;
std::set<RTLIL::SigSpec> handled_sig;
@ -124,14 +124,14 @@ struct OptReduceWorker
if (this_s.size() > 1)
{
RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, "$reduce_or");
reduce_or_cell->set("\\A", this_s);
reduce_or_cell->setPort("\\A", this_s);
reduce_or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.size());
reduce_or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID);
this_s = RTLIL::SigSpec(reduce_or_wire);
reduce_or_cell->set("\\Y", this_s);
reduce_or_cell->setPort("\\Y", this_s);
}
new_sig_b.append(this_b);
@ -148,14 +148,14 @@ struct OptReduceWorker
if (new_sig_s.size() == 0)
{
module->connect(RTLIL::SigSig(cell->get("\\Y"), cell->get("\\A")));
assign_map.add(cell->get("\\Y"), cell->get("\\A"));
module->connect(RTLIL::SigSig(cell->getPort("\\Y"), cell->getPort("\\A")));
assign_map.add(cell->getPort("\\Y"), cell->getPort("\\A"));
module->remove(cell);
}
else
{
cell->set("\\B", new_sig_b);
cell->set("\\S", new_sig_s);
cell->setPort("\\B", new_sig_b);
cell->setPort("\\S", new_sig_s);
if (new_sig_s.size() > 1) {
cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.size());
} else {
@ -167,9 +167,9 @@ struct OptReduceWorker
void opt_mux_bits(RTLIL::Cell *cell)
{
std::vector<RTLIL::SigBit> sig_a = assign_map(cell->get("\\A")).to_sigbit_vector();
std::vector<RTLIL::SigBit> sig_b = assign_map(cell->get("\\B")).to_sigbit_vector();
std::vector<RTLIL::SigBit> sig_y = assign_map(cell->get("\\Y")).to_sigbit_vector();
std::vector<RTLIL::SigBit> sig_a = assign_map(cell->getPort("\\A")).to_sigbit_vector();
std::vector<RTLIL::SigBit> sig_b = assign_map(cell->getPort("\\B")).to_sigbit_vector();
std::vector<RTLIL::SigBit> sig_y = assign_map(cell->getPort("\\Y")).to_sigbit_vector();
std::vector<RTLIL::SigBit> new_sig_y;
RTLIL::SigSig old_sig_conn;
@ -210,29 +210,29 @@ struct OptReduceWorker
if (new_sig_y.size() != sig_y.size())
{
log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str());
log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->get("\\A")),
log_signal(cell->get("\\B")), log_signal(cell->get("\\Y")));
log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort("\\A")),
log_signal(cell->getPort("\\B")), log_signal(cell->getPort("\\Y")));
cell->set("\\A", RTLIL::SigSpec());
cell->setPort("\\A", RTLIL::SigSpec());
for (auto &in_tuple : consolidated_in_tuples) {
RTLIL::SigSpec new_a = cell->get("\\A");
RTLIL::SigSpec new_a = cell->getPort("\\A");
new_a.append(in_tuple.at(0));
cell->set("\\A", new_a);
cell->setPort("\\A", new_a);
}
cell->set("\\B", RTLIL::SigSpec());
for (int i = 1; i <= cell->get("\\S").size(); i++)
cell->setPort("\\B", RTLIL::SigSpec());
for (int i = 1; i <= cell->getPort("\\S").size(); i++)
for (auto &in_tuple : consolidated_in_tuples) {
RTLIL::SigSpec new_b = cell->get("\\B");
RTLIL::SigSpec new_b = cell->getPort("\\B");
new_b.append(in_tuple.at(i));
cell->set("\\B", new_b);
cell->setPort("\\B", new_b);
}
cell->parameters["\\WIDTH"] = RTLIL::Const(new_sig_y.size());
cell->set("\\Y", new_sig_y);
cell->setPort("\\Y", new_sig_y);
log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->get("\\A")),
log_signal(cell->get("\\B")), log_signal(cell->get("\\Y")));
log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort("\\A")),
log_signal(cell->getPort("\\B")), log_signal(cell->getPort("\\Y")));
log(" New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second));
module->connect(old_sig_conn);
@ -256,14 +256,14 @@ struct OptReduceWorker
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == "$mem")
mem_wren_sigs.add(assign_map(cell->get("\\WR_EN")));
mem_wren_sigs.add(assign_map(cell->getPort("\\WR_EN")));
if (cell->type == "$memwr")
mem_wren_sigs.add(assign_map(cell->get("\\EN")));
mem_wren_sigs.add(assign_map(cell->getPort("\\EN")));
}
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == "$dff" && mem_wren_sigs.check_any(assign_map(cell->get("\\Q"))))
mem_wren_sigs.add(assign_map(cell->get("\\D")));
if (cell->type == "$dff" && mem_wren_sigs.check_any(assign_map(cell->getPort("\\Q"))))
mem_wren_sigs.add(assign_map(cell->getPort("\\D")));
}
bool keep_expanding_mem_wren_sigs = true;
@ -271,12 +271,12 @@ struct OptReduceWorker
keep_expanding_mem_wren_sigs = false;
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->get("\\Y")))) {
if (!mem_wren_sigs.check_all(assign_map(cell->get("\\A"))) ||
!mem_wren_sigs.check_all(assign_map(cell->get("\\B"))))
if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->getPort("\\Y")))) {
if (!mem_wren_sigs.check_all(assign_map(cell->getPort("\\A"))) ||
!mem_wren_sigs.check_all(assign_map(cell->getPort("\\B"))))
keep_expanding_mem_wren_sigs = true;
mem_wren_sigs.add(assign_map(cell->get("\\A")));
mem_wren_sigs.add(assign_map(cell->get("\\B")));
mem_wren_sigs.add(assign_map(cell->getPort("\\A")));
mem_wren_sigs.add(assign_map(cell->getPort("\\B")));
}
}
}
@ -298,7 +298,7 @@ struct OptReduceWorker
RTLIL::Cell *cell = cell_it.second;
if (cell->type != type || !design->selected(module, cell))
continue;
drivers.insert(assign_map(cell->get("\\Y")), cell);
drivers.insert(assign_map(cell->getPort("\\Y")), cell);
cells.insert(cell);
}
@ -320,7 +320,7 @@ struct OptReduceWorker
{
// this optimization is to aggressive for most coarse-grain applications.
// but we always want it for multiplexers driving write enable ports.
if (do_fine || mem_wren_sigs.check_any(assign_map(cell->get("\\Y"))))
if (do_fine || mem_wren_sigs.check_any(assign_map(cell->getPort("\\Y"))))
opt_mux_bits(cell);
opt_mux(cell);

36
passes/opt/opt_rmdff.cc
View file

@ -33,34 +33,34 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
RTLIL::Const val_cp, val_rp, val_rv;
if (dff->type == "$_DFF_N_" || dff->type == "$_DFF_P_") {
sig_d = dff->get("\\D");
sig_q = dff->get("\\Q");
sig_c = dff->get("\\C");
sig_d = dff->getPort("\\D");
sig_q = dff->getPort("\\Q");
sig_c = dff->getPort("\\C");
val_cp = RTLIL::Const(dff->type == "$_DFF_P_", 1);
}
else if (dff->type.substr(0,6) == "$_DFF_" && dff->type.substr(9) == "_" &&
(dff->type[6] == 'N' || dff->type[6] == 'P') &&
(dff->type[7] == 'N' || dff->type[7] == 'P') &&
(dff->type[8] == '0' || dff->type[8] == '1')) {
sig_d = dff->get("\\D");
sig_q = dff->get("\\Q");
sig_c = dff->get("\\C");
sig_r = dff->get("\\R");
sig_d = dff->getPort("\\D");
sig_q = dff->getPort("\\Q");
sig_c = dff->getPort("\\C");
sig_r = dff->getPort("\\R");
val_cp = RTLIL::Const(dff->type[6] == 'P', 1);
val_rp = RTLIL::Const(dff->type[7] == 'P', 1);
val_rv = RTLIL::Const(dff->type[8] == '1', 1);
}
else if (dff->type == "$dff") {
sig_d = dff->get("\\D");
sig_q = dff->get("\\Q");
sig_c = dff->get("\\CLK");
sig_d = dff->getPort("\\D");
sig_q = dff->getPort("\\Q");
sig_c = dff->getPort("\\CLK");
val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1);
}
else if (dff->type == "$adff") {
sig_d = dff->get("\\D");
sig_q = dff->get("\\Q");
sig_c = dff->get("\\CLK");
sig_r = dff->get("\\ARST");
sig_d = dff->getPort("\\D");
sig_q = dff->getPort("\\Q");
sig_c = dff->getPort("\\CLK");
sig_r = dff->getPort("\\ARST");
val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1);
val_rp = RTLIL::Const(dff->parameters["\\ARST_POLARITY"].as_bool(), 1);
val_rv = dff->parameters["\\ARST_VALUE"];
@ -85,8 +85,8 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
std::set<RTLIL::Cell*> muxes;
mux_drivers.find(sig_d, muxes);
for (auto mux : muxes) {
RTLIL::SigSpec sig_a = assign_map(mux->get("\\A"));
RTLIL::SigSpec sig_b = assign_map(mux->get("\\B"));
RTLIL::SigSpec sig_a = assign_map(mux->getPort("\\A"));
RTLIL::SigSpec sig_b = assign_map(mux->getPort("\\B"));
if (sig_a == sig_q && sig_b.is_fully_const()) {
RTLIL::SigSig conn(sig_q, sig_b);
mod->connect(conn);
@ -181,8 +181,8 @@ struct OptRmdffPass : public Pass {
std::vector<std::string> dff_list;
for (auto &it : mod_it.second->cells_) {
if (it.second->type == "$mux" || it.second->type == "$pmux") {
if (it.second->get("\\A").size() == it.second->get("\\B").size())
mux_drivers.insert(assign_map(it.second->get("\\Y")), it.second);
if (it.second->getPort("\\A").size() == it.second->getPort("\\B").size())
mux_drivers.insert(assign_map(it.second->getPort("\\Y")), it.second);
continue;
}
if (!design->selected(mod_it.second, it.second))

6
passes/opt/opt_share.cc
View file

@ -179,8 +179,8 @@ struct OptShareWorker
}
if (cell1->type.substr(0, 1) == "$" && conn1.count("\\Q") != 0) {
std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->get("\\Q")).to_sigbit_vector();
std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->get("\\Q")).to_sigbit_vector();
std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort("\\Q")).to_sigbit_vector();
std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort("\\Q")).to_sigbit_vector();
for (size_t i = 0; i < q1.size(); i++)
if ((q1.at(i).wire == NULL || q2.at(i).wire == NULL) && q1.at(i) != q2.at(i)) {
lt = q1.at(i) < q2.at(i);
@ -262,7 +262,7 @@ struct OptShareWorker
log(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str());
for (auto &it : cell->connections()) {
if (ct.cell_output(cell->type, it.first)) {
RTLIL::SigSpec other_sig = sharemap[cell]->get(it.first);
RTLIL::SigSpec other_sig = sharemap[cell]->getPort(it.first);
log(" Redirecting output %s: %s = %s\n", it.first.c_str(),
log_signal(it.second), log_signal(other_sig));
module->connect(RTLIL::SigSig(it.second, other_sig));