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Renamed port access function on RTLIL::Cell, added param access functions

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This commit is contained in:
Clifford Wolf 2014-07-31 16:38:54 +02:00
parent b5a9e51b96
commit cdae8abe16
46 changed files with 1086 additions and 1059 deletions
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2
passes/hierarchy/submod.cc
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@ -185,7 +185,7 @@ struct SubmodWorker
RTLIL::Wire *old_wire = it.first;
RTLIL::Wire *new_wire = it.second.new_wire;
if (new_wire->port_id > 0)
new_cell->set(new_wire->name, RTLIL::SigSpec(old_wire));
new_cell->setPort(new_wire->name, RTLIL::SigSpec(old_wire));
}
}