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https://github.com/YosysHQ/yosys
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abc9_ops: add and use new TimingInfo struct
This commit is contained in:
Eddie Hung
parent
bc97e64b21
commit
cda4acb544
2 changed files with 214 additions and 70 deletions
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@ -22,6 +22,7 @@
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#include "kernel/sigtools.h"
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#include "kernel/utils.h"
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#include "kernel/celltypes.h"
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#include "kernel/timinginfo.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -380,9 +381,8 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
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void prep_delays(RTLIL::Design *design, bool dff_mode)
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{
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// Derive and collect all Yosys blackbox modules that are not combinatorial abc9 boxes
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// Derive all Yosys blackbox modules that are not combinatorial abc9 boxes
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// (e.g. DSPs, RAMs, etc.) nor abc9 flops and collect all such instantiations
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pool<Module*> blackboxes;
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pool<Module*> flops;
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std::vector<Cell*> cells;
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for (auto module : design->selected_modules()) {
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@ -405,7 +405,6 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
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IdString blackboxes_type = inst_module->derive(design, cell->parameters);
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inst_module = design->module(blackboxes_type);
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log_assert(inst_module);
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blackboxes.insert(inst_module);
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if (dff_mode && inst_module->get_bool_attribute(ID(abc9_flop))) {
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flops.insert(inst_module);
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@ -417,70 +416,33 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
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}
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}
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const TimingInfo timing(design);
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// Transform all $specify3 and $specrule to abc9_{arrival,required} attributes
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dict<SigBit, int> arrivals, requireds;
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// TODO: Deprecate
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pool<Wire*> ports;
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std::stringstream ss;
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for (auto module : blackboxes) {
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arrivals.clear();
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requireds.clear();
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for (auto cell : module->cells()) {
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if (cell->type == ID($specify3)) {
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auto src = cell->getPort(ID(SRC));
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auto dst = cell->getPort(ID(DST));
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for (const auto &c : src.chunks())
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if (!c.wire->port_input)
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log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
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for (const auto &c : dst.chunks())
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if (!c.wire->port_output)
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log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
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int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
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int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
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int max = std::max(rise_max,fall_max);
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if (max < 0)
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log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
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if (max <= 0) {
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log_debug("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX <= 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
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continue;
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}
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for (const auto &d : dst)
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arrivals[d] = std::max(arrivals[d], max);
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}
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else if (cell->type == ID($specrule)) {
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auto type = cell->getParam(ID(TYPE)).decode_string();
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if (type != "$setup" && type != "$setuphold")
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continue;
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auto src = cell->getPort(ID(SRC));
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auto dst = cell->getPort(ID(DST));
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for (const auto &c : src.chunks())
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if (!c.wire->port_input)
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log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
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for (const auto &c : dst.chunks())
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if (!c.wire->port_input)
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log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dst));
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int setup = cell->getParam(ID(T_LIMIT_MAX)).as_int();
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if (setup < 0)
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log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
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if (setup <= 0) {
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log_debug("Module '%s' contains specify cell '%s' with T_LIMIT_MAX <= 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
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continue;
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}
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for (const auto &s : src)
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requireds[s] = std::max(requireds[s], setup);
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}
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}
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for (auto module : design->modules()) {
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if (arrivals.empty() && requireds.empty())
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continue;
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auto it = timing.data.find(module->name);
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if (it == timing.data.end())
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continue;
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const auto &t = it->second;
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if (t.arrival.empty() && t.required.empty())
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continue;
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const auto &arrival = t.arrival;
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const auto &required = t.required;
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ports.clear();
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for (const auto &i : arrivals)
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for (const auto &i : arrival)
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ports.insert(i.first.wire);
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for (auto wire : ports) {
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log_assert(wire->port_output);
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ss.str("");
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if (GetSize(wire) == 1)
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wire->attributes[ID(abc9_arrival)] = arrivals.at(SigBit(wire,0));
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wire->attributes[ID(abc9_arrival)] = arrival.at(SigBit(wire,0));
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else {
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bool first = true;
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for (auto b : SigSpec(wire)) {
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@ -488,24 +450,20 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
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first = false;
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else
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ss << " ";
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auto it = arrivals.find(b);
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if (it == arrivals.end())
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ss << "0";
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else
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ss << it->second;
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ss << arrival.at(b, 0);
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}
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wire->attributes[ID(abc9_arrival)] = ss.str();
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}
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}
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ports.clear();
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for (const auto &i : requireds)
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for (const auto &i : required)
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ports.insert(i.first.wire);
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for (auto wire : ports) {
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log_assert(wire->port_input);
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ss.str("");
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if (GetSize(wire) == 1)
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wire->attributes[ID(abc9_required)] = requireds.at(SigBit(wire,0));
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wire->attributes[ID(abc9_required)] = required.at(SigBit(wire,0));
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else {
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bool first = true;
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for (auto b : SigSpec(wire)) {
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@ -513,11 +471,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
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first = false;
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else
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ss << " ";
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auto it = requireds.find(b);
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if (it == requireds.end())
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ss << "0";
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else
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ss << it->second;
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ss << required.at(b, 0);
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}
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wire->attributes[ID(abc9_required)] = ss.str();
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}
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@ -567,7 +521,8 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
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#ifndef NDEBUG
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if (ys_debug(1)) {
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static std::set<std::pair<IdString,IdString>> seen;
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if (seen.emplace(derived_type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), requireds[i]);
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if (seen.emplace(derived_type, conn.first).second) log("%s.%s abc9_required = '%s'\n", log_id(cell->type), log_id(conn.first),
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port_wire->attributes.at("\\abc9_required").decode_string().c_str());
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}
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#endif
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auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));
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@ -659,6 +614,7 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
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auto abc9_flop = module->get_bool_attribute(ID(abc9_flop));
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if (abc9_flop) {
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if (dff_mode) {
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log_dump(module->name);
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int num_inputs = 0, num_outputs = 0;
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for (auto port_name : module->ports) {
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auto wire = module->wire(port_name);
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@ -699,7 +655,22 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
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first = false;
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else
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ss << " ";
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ss << wire->attributes.at("\\abc9_required", 0).as_int();
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auto it = wire->attributes.find("\\abc9_required");
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if (it == wire->attributes.end())
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ss << 0;
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else {
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log_assert(it->second.flags == 0);
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ss << it->second.as_int();
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#ifndef NDEBUG
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if (ys_debug(1)) {
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static std::set<std::pair<IdString,IdString>> seen;
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if (seen.emplace(module->name, port_name).second) log("%s.%s abc9_required = %d\n", log_id(module),
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log_id(port_name), it->second.as_int());
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}
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#endif
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}
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}
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// Last input is 'abc9_ff.Q'
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ss << " 0" << std::endl << std::endl;
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