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https://github.com/YosysHQ/yosys
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Implemented read_verilog -defer
This commit is contained in:
Clifford Wolf
parent
b463907890
commit
cd9e8741a7
4 changed files with 111 additions and 68 deletions
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@ -747,14 +747,18 @@ bool AstNode::asBool()
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}
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// create a new AstModule from an AST_MODULE AST node
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static AstModule* process_module(AstNode *ast)
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static AstModule* process_module(AstNode *ast, bool defer)
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{
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assert(ast->type == AST_MODULE);
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log("Generating RTLIL representation for module `%s'.\n", ast->str.c_str());
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if (defer)
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log("Storing AST representation for module `%s'.\n", ast->str.c_str());
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else
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log("Generating RTLIL representation for module `%s'.\n", ast->str.c_str());
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current_module = new AstModule;
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current_module->ast = NULL;
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current_module->name = ast->str;
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current_module->name = defer ? "$abstract" + ast->str : ast->str;
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current_module->attributes["\\src"] = stringf("%s:%d", ast->filename.c_str(), ast->linenum);
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current_ast_mod = ast;
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@ -766,61 +770,64 @@ static AstModule* process_module(AstNode *ast)
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log("--- END OF AST DUMP ---\n");
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}
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while (ast->simplify(!flag_noopt, false, false, 0, -1, false)) { }
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if (!defer)
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{
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while (ast->simplify(!flag_noopt, false, false, 0, -1, false)) { }
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if (flag_dump_ast2) {
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log("Dumping verilog AST after simplification:\n");
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ast->dumpAst(NULL, " ");
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log("--- END OF AST DUMP ---\n");
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}
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if (flag_dump_vlog) {
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log("Dumping verilog AST (as requested by dump_vlog option):\n");
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ast->dumpVlog(NULL, " ");
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log("--- END OF AST DUMP ---\n");
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}
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if (flag_lib) {
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std::vector<AstNode*> new_children;
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for (auto child : ast->children) {
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if (child->type == AST_WIRE && (child->is_input || child->is_output))
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new_children.push_back(child);
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else
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delete child;
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if (flag_dump_ast2) {
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log("Dumping verilog AST after simplification:\n");
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ast->dumpAst(NULL, " ");
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log("--- END OF AST DUMP ---\n");
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}
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ast->children.swap(new_children);
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ast->attributes["\\blackbox"] = AstNode::mkconst_int(1, false);
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}
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ignoreThisSignalsInInitial = RTLIL::SigSpec();
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if (flag_dump_vlog) {
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log("Dumping verilog AST (as requested by dump_vlog option):\n");
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ast->dumpVlog(NULL, " ");
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log("--- END OF AST DUMP ---\n");
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}
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for (auto &attr : ast->attributes) {
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if (attr.second->type != AST_CONSTANT)
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log_error("Attribute `%s' with non-constant value at %s:%d!\n",
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attr.first.c_str(), ast->filename.c_str(), ast->linenum);
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current_module->attributes[attr.first] = attr.second->asAttrConst();
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}
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for (size_t i = 0; i < ast->children.size(); i++) {
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AstNode *node = ast->children[i];
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if (node->type == AST_WIRE || node->type == AST_MEMORY)
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node->genRTLIL();
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}
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for (size_t i = 0; i < ast->children.size(); i++) {
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AstNode *node = ast->children[i];
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if (node->type != AST_WIRE && node->type != AST_MEMORY && node->type != AST_INITIAL)
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node->genRTLIL();
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}
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if (flag_lib) {
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std::vector<AstNode*> new_children;
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for (auto child : ast->children) {
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if (child->type == AST_WIRE && (child->is_input || child->is_output))
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new_children.push_back(child);
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else
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delete child;
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}
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ast->children.swap(new_children);
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ast->attributes["\\blackbox"] = AstNode::mkconst_int(1, false);
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}
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ignoreThisSignalsInInitial.sort_and_unify();
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ignoreThisSignalsInInitial = RTLIL::SigSpec();
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for (size_t i = 0; i < ast->children.size(); i++) {
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AstNode *node = ast->children[i];
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if (node->type == AST_INITIAL)
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node->genRTLIL();
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for (auto &attr : ast->attributes) {
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if (attr.second->type != AST_CONSTANT)
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log_error("Attribute `%s' with non-constant value at %s:%d!\n",
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attr.first.c_str(), ast->filename.c_str(), ast->linenum);
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current_module->attributes[attr.first] = attr.second->asAttrConst();
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}
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for (size_t i = 0; i < ast->children.size(); i++) {
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AstNode *node = ast->children[i];
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if (node->type == AST_WIRE || node->type == AST_MEMORY)
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node->genRTLIL();
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}
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for (size_t i = 0; i < ast->children.size(); i++) {
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AstNode *node = ast->children[i];
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if (node->type != AST_WIRE && node->type != AST_MEMORY && node->type != AST_INITIAL)
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node->genRTLIL();
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}
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ignoreThisSignalsInInitial.sort_and_unify();
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for (size_t i = 0; i < ast->children.size(); i++) {
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AstNode *node = ast->children[i];
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if (node->type == AST_INITIAL)
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node->genRTLIL();
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}
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ignoreThisSignalsInInitial = RTLIL::SigSpec();
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}
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ignoreThisSignalsInInitial = RTLIL::SigSpec();
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current_module->ast = ast_before_simplify;
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current_module->nolatches = flag_nolatches;
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current_module->nomem2reg = flag_nomem2reg;
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@ -832,7 +839,7 @@ static AstModule* process_module(AstNode *ast)
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}
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// create AstModule instances for all modules in the AST tree and add them to 'design'
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void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef)
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void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer)
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{
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current_ast = ast;
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flag_dump_ast1 = dump_ast1;
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@ -847,7 +854,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
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assert(current_ast->type == AST_DESIGN);
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for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++) {
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if (design->modules.count((*it)->str) != 0) {
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if (design->modules.count((*it)->str) != 0 && design->modules.count("$abstract" + (*it)->str) != 0) {
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if (!ignore_redef)
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log_error("Re-definition of module `%s' at %s:%d!\n",
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(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
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@ -855,7 +862,10 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
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(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
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continue;
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}
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design->modules[(*it)->str] = process_module(*it);
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if (defer)
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design->modules["$abstract" + (*it)->str] = process_module(*it, true);
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else
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design->modules[(*it)->str] = process_module(*it, false);
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}
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}
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@ -869,7 +879,12 @@ AstModule::~AstModule()
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// create a new parametric module (when needed) and return the name of the generated module
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RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters)
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{
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log_header("Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", name.c_str());
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std::string stripped_name = name;
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if (stripped_name.substr(0, 9) == "$abstract")
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stripped_name = stripped_name.substr(9);
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log_header("Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str());
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current_ast = NULL;
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flag_dump_ast1 = false;
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@ -885,12 +900,13 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdStrin
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std::string para_info;
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std::vector<unsigned char> hash_data;
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hash_data.insert(hash_data.end(), name.begin(), name.end());
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hash_data.insert(hash_data.end(), stripped_name.begin(), stripped_name.end());
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hash_data.push_back(0);
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AstNode *new_ast = ast->clone();
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int para_counter = 0;
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int orig_parameters_n = parameters.size();
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for (auto it = new_ast->children.begin(); it != new_ast->children.end(); it++) {
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AstNode *child = *it;
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if (child->type != AST_PARAMETER)
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@ -917,10 +933,15 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdStrin
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}
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}
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if (parameters.size() > 0)
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log_error("Requested parameter `%s' does not exist in module `%s'!\n", parameters.begin()->first.c_str(), name.c_str());
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log_error("Requested parameter `%s' does not exist in module `%s'!\n", parameters.begin()->first.c_str(), stripped_name.c_str());
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std::string modname;
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if (orig_parameters_n == 0)
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{
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modname = stripped_name;
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}
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else
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if (para_info.size() > 60)
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{
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unsigned char hash[20];
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@ -933,16 +954,16 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdStrin
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char hexstring[41];
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sha1::toHexString(hash, hexstring);
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modname = "$paramod$" + std::string(hexstring) + name;
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modname = "$paramod$" + std::string(hexstring) + stripped_name;
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}
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else
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{
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modname = "$paramod" + name + para_info;
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modname = "$paramod" + stripped_name + para_info;
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}
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if (design->modules.count(modname) == 0) {
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new_ast->str = modname;
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design->modules[modname] = process_module(new_ast);
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design->modules[modname] = process_module(new_ast, false);
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design->modules[modname]->check();
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} else {
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log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
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