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write_xaiger: fix for (* keep *) on flop output

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This commit is contained in:
Eddie Hung 2020-01-21 09:43:04 -08:00
parent d4e188299b
commit cd8f55a911
2 changed files with 18 additions and 3 deletions
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6
backends/aiger/xaiger.cc
View file

@ -222,6 +222,8 @@ struct XAigerWriter
alias_map[Q] = D; alias_map[Q] = D;
auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell)); auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell));
log_assert(r.second); log_assert(r.second);
if (input_bits.erase(Q))
log_assert(Q.wire->attributes.count(ID::keep));
continue; continue;
} }
@ -568,9 +570,6 @@ struct XAigerWriter
// write_o_buffer(0); // write_o_buffer(0);
if (!box_list.empty() || !ff_bits.empty()) { if (!box_list.empty() || !ff_bits.empty()) {
RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
log_assert(holes_module);
dict<IdString, std::tuple<int,int,int>> cell_cache; dict<IdString, std::tuple<int,int,int>> cell_cache;
int box_count = 0; int box_count = 0;
@ -653,6 +652,7 @@ struct XAigerWriter
f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be)); f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
f.write(buffer_str.data(), buffer_str.size()); f.write(buffer_str.data(), buffer_str.size());
RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
if (holes_module) { if (holes_module) {
std::stringstream a_buffer; std::stringstream a_buffer;
XAigerWriter writer(holes_module, true /* holes_mode */); XAigerWriter writer(holes_module, true /* holes_mode */);

15
tests/various/abc9.ys
View file

@ -14,6 +14,7 @@ design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter sat -verify -prove-asserts -show-ports miter
design -load read design -load read
hierarchy -top abc9_test028 hierarchy -top abc9_test028
proc proc
@ -23,6 +24,7 @@ select -assert-count 1 t:$lut r:LUT=2'b01 r:WIDTH=1 %i %i
select -assert-count 1 t:unknown select -assert-count 1 t:unknown
select -assert-none t:$lut t:unknown %% t: %D select -assert-none t:$lut t:unknown %% t: %D
design -load read design -load read
hierarchy -top abc9_test032 hierarchy -top abc9_test032
proc proc
@ -38,3 +40,16 @@ design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -seq 10 -verify -prove-asserts -show-ports miter sat -seq 10 -verify -prove-asserts -show-ports miter
design -reset
read_verilog -icells <<EOT
module abc9_test036(input clk, d, output q);
(* keep *) reg w;
$__ABC9_FF_ ff(.D(d), .Q(w));
wire \ff.clock = clk;
wire \ff.init = 1'b0;
assign q = w;
endmodule
EOT
abc9 -lut 4 -dff