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fixed typos

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This commit is contained in:
Johann Glaser 2013-03-17 22:02:30 +01:00 • committed by Clifford Wolf
parent ba3793b642
commit cd8008bda0
12 changed files with 26 additions and 26 deletions
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6
passes/abc/abc.cc
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@ -638,9 +638,9 @@ struct AbcPass : public Pass {
log("\n");
log(" -liberty <file>\n");
log(" generate netlists for the specified cell library (using the liberty\n");
log(" file format). This option is ignored if also -script option is also\n");
log(" used. Without this option, ABC is used to optimize the netlist but\n");
log(" keeps using yosys's internal gate library.\n");
log(" file format). Without this option, ABC is used to optimize the netlist\n");
log(" but keeps using yosys's internal gate library. This option is ignored if\n");
log(" the -script option is also used.\n");
log("\n");
log(" -nocleanup\n");
log(" when this option is used, the temporary files created by this pass\n");

6
passes/fsm/fsm_detect.cc
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@ -116,14 +116,14 @@ struct FsmDetectPass : public Pass {
log("\n");
log(" fsm_detect [selection]\n");
log("\n");
log("This pass detects finite state machine by identifying the state signal.\n");
log("This pass detects finite state machines by identifying the state signal.\n");
log("The state signal is then marked by setting the attribute 'fsm_encoding'\n");
log("on the state signal to \"auto\".\n");
log("\n");
log("Existing 'fsm_encoding' attributes are not changed by this pass.\n");
log("\n");
log("Signals can be protected from beeing detected by this pass by setting the\n");
log("'fsm_encoding' atrribute to \"none\".\n");
log("Signals can be protected from being detected by this pass by setting the\n");
log("'fsm_encoding' attribute to \"none\".\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)

2
passes/fsm/fsm_expand.cc
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@ -241,7 +241,7 @@ struct FsmExpandPass : public Pass {
log("\n");
log(" fsm_expand [selection]\n");
log("\n");
log("The fsm_extract pass is conservative about the cells that belong the a finate\n");
log("The fsm_extract pass is conservative about the cells that belong to a finite\n");
log("state machine. This pass can be used to merge additional auxiliary gates into\n");
log("the finate state machine.\n");
log("\n");

2
passes/opt/opt_muxtree.cc
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@ -406,7 +406,7 @@ struct OptMuxtreePass : public Pass {
log(" opt_muxtree [selection]\n");
log("\n");
log("This pass analyzes the control signals for the multiplexer trees in the design\n");
log("and identifies inputs that can never be active. In then removes this dead\n");
log("and identifies inputs that can never be active. It then removes this dead\n");
log("branches from the multiplexer trees.\n");
log("\n");
log("This pass only operates on completely selected modules without processes.\n");

6
passes/opt/opt_rmunused.cc
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@ -242,9 +242,9 @@ struct OptRmUnusedPass : public Pass {
log(" opt_rmunused [selection]\n");
log("\n");
log("This pass identifies wires and cells that are unused and removes them. Other\n");
log("often remove cells but leave the wires in the design or reconnect the wires\n");
log("but leave the old cells in the design. This pass can be used to clean up after\n");
log("the passes that do the actual work.\n");
log("passes often remove cells but leave the wires in the design or reconnect the\n");
log("wires but leave the old cells in the design. This pass can be used to clean up\n");
log("after the passes that do the actual work.\n");
log("\n");
log("This pass only operates on completely selected modules without processes.\n");
log("\n");

4
passes/proc/proc_dff.cc
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@ -168,8 +168,8 @@ struct ProcDffPass : public Pass {
log("\n");
log(" proc_dff [selection]\n");
log("\n");
log("This pass identifies flip-flops in the processes and converts then to\n");
log("flip-flop cells.\n");
log("This pass identifies flip-flops in the processes and converts them to\n");
log("d-type flip-flop cells.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)

2
passes/scc/scc.cc
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@ -211,7 +211,7 @@ struct SccPass : public Pass {
log("\n");
log(" -max_depth <num>\n");
log(" limit to loops not longer than the specified number of cells. This can\n");
log(" e.g. be usefull in identifying local loops in a module that turns out\n");
log(" e.g. be useful in identifying local loops in a module that turns out\n");
log(" to be one gigantic SCC.\n");
log("\n");
log(" -all_cell_types\n");

4
passes/submod/submod.cc
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@ -239,7 +239,7 @@ struct SubmodWorker
};
struct SubmodPass : public Pass {
SubmodPass() : Pass("submod", "moving part of a module to a new submodle") { }
SubmodPass() : Pass("submod", "moving part of a module to a new submodule") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
@ -259,7 +259,7 @@ struct SubmodPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing SUBMOD pass (moving cells to submodes as requested).\n");
log_header("Executing SUBMOD pass (moving cells to submodules as requested).\n");
log_push();
Pass::call(design, "opt_rmunused");

4
passes/techmap/techmap.cc
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@ -172,14 +172,14 @@ struct TechmapPass : public Pass {
log("\n");
log(" techmap [-map filename] [selection]\n");
log("\n");
log("This pass implements a very simple technology mapper than replaces cells in\n");
log("This pass implements a very simple technology mapper that replaces cells in\n");
log("the design with implementations given in form of a verilog or ilang source\n");
log("file.\n");
log("\n");
log(" -map filename\n");
log(" the library of cell implementations to be used.\n");
log(" without this parameter a builtin library is used that\n");
log(" transform the internal RTL cells to the internal gate\n");
log(" transforms the internal RTL cells to the internal gate\n");
log(" library.\n");
log("\n");
log("See 'help extract' for a pass that does the opposite thing.\n");