Reinstate #4768

Revert the reversion so that we can fix the bugs that the PR missed.

tests/select/boxes.v

@@ -1,4 +1,3 @@
-read_verilog -specify <<EOT
 module top(input a, b, output o);
 assign o = a & b;
 endmodule
@@ -15,14 +14,3 @@ endmodule
 module wb(input a, b, output o);
 assign o = a ^ b;
 endmodule
-EOT
-clean
-
-select -assert-count 1 c:*
-select -assert-none t:* t:$and %d
-select -assert-count 3 w:*
-select -assert-count 4 *
-
-select -assert-count 3 =c:*
-select -assert-count 10 =w:*
-select -assert-count 13 =*

tests/select/boxes_equals_clean.ys

@@ -0,0 +1,7 @@
+read_verilog -specify boxes.v
+clean
+
+logger -expect-no-warnings
+select -assert-count 5 =wb
+clean =wb
+select -assert-count 4 =wb

tests/select/boxes_equals_name.ys

@@ -0,0 +1,7 @@
+read_verilog -specify boxes.v
+clean
+
+select -set top top
+select -assert-count 4 @top
+select -set boxes =?b
+select -assert-count 9 @boxes

tests/select/boxes_equals_operators.ys

@@ -0,0 +1,38 @@
+read_verilog -specify boxes.v
+clean
+
+# wb = 4w1c, bb = 3w1c, top = 3w1c
+select =wb
+select -assert-count 5 %
+select -add =bb
+select -assert-count 9 %
+select -del =wb
+select -assert-count 4 %
+
+# unions
+select -assert-count 8 =bb * %u
+select -assert-count 8 * =bb %u
+select -assert-count 13 top =* %u
+select -assert-count 8 =bb top %u
+select -assert-count 8 top =bb %u
+
+# intersections
+select -assert-count 3 =w:* =bb %i
+select -assert-count 4 =* * %i
+select -assert-count 4 * =* %i
+
+# inverses
+select -assert-count 8 =wb %n
+select -assert-none top %n
+select -assert-none * %n
+select -assert-none =* %n
+select -assert-count 9 =top %n
+
+# differences
+select -assert-count 9 =* top %d
+select -assert-count 0 top =* %d
+select -assert-count 9 =* * %d
+select -assert-count 0 * =* %d
+
+# random
+select -assert-any =?b %R

tests/select/boxes_equals_pattern.ys

@@ -0,0 +1,7 @@
+read_verilog -specify boxes.v
+clean
+
+select -assert-none ?b
+select -assert-count 4 =bb
+select -assert-count 5 =wb
+select -assert-count 9 =?b

tests/select/boxes_equals_wildcard.ys

@@ -0,0 +1,6 @@
+read_verilog -specify boxes.v
+clean
+
+select -assert-count 3 =c:*
+select -assert-count 10 =w:*
+select -assert-count 13 =*

tests/select/boxes_no_equals.ys

@@ -0,0 +1,7 @@
+read_verilog -specify boxes.v
+clean
+
+select -assert-count 1 c:*
+select -assert-none t:* t:$and %d
+select -assert-count 3 w:*
+select -assert-count 4 *

tests/select/boxes_no_equals_clean.ys

@@ -0,0 +1,18 @@
+read_verilog -specify boxes.v
+
+logger -expect warning "did not match any module" 2
+clean wb
+opt_clean wb
+logger -check-expected
+
+select -clear
+logger -expect warning "did not match any module" 2
+clean wb
+opt_clean wb
+logger -check-expected
+
+select -none
+logger -expect warning "did not match any module" 2
+clean wb
+opt_clean wb
+logger -check-expected

tests/select/boxes_stack.ys

@@ -0,0 +1,29 @@
+read_verilog -specify boxes.v
+clean
+
+# default selection == select *
+select -assert-count 4 *
+select -assert-count 4 %
+
+# -none replaces default selection
+select -none
+select -assert-none %
+select -assert-count 13 =*
+
+# select replaces current selection
+select =*
+select -assert-count 13 %
+
+# -module changes module
+select -module wb
+select -assert-none %
+select -assert-count 5 =*
+
+# -none maintains module
+select -none
+select -assert-count 5 =*
+
+# -clear clears current selection and module
+select -clear
+select -assert-count 4 %
+select -assert-count 13 =*