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Reinstate #4768

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Revert the reversion so that we can fix the bugs that the PR missed.
This commit is contained in:
Krystine Sherwin 2025-04-08 11:57:43 +12:00
parent bf386feba7
commit cd3b914132
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38 changed files with 700 additions and 263 deletions
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208
kernel/rtlil.h
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@ -56,8 +56,33 @@ namespace RTLIL
CONST_FLAG_REAL = 4 // only used for parameters
};
enum SelectPartials : unsigned char {
SELECT_ALL = 0, // include partial modules
SELECT_WHOLE_ONLY = 1, // ignore partial modules
SELECT_WHOLE_WARN = 2, // call log_warning on partial module
SELECT_WHOLE_ERR = 3, // call log_error on partial module
SELECT_WHOLE_CMDERR = 4 // call log_cmd_error on partial module
};
enum SelectBoxes : unsigned char {
SB_ALL = 0, // include boxed modules
SB_WARN = 1, // helper for log_warning
SB_ERR = 2, // helper for log_error
SB_CMDERR = 3, // helper for log_cmd_error
SB_UNBOXED_ONLY = 4, // ignore boxed modules
SB_UNBOXED_WARN = 5, // call log_warning on boxed module
SB_UNBOXED_ERR = 6, // call log_error on boxed module
SB_UNBOXED_CMDERR = 7, // call log_cmd_error on boxed module
SB_INCL_WB = 8, // helper for white boxes
SB_EXCL_BB_ONLY = 12, // ignore black boxes, but not white boxes
SB_EXCL_BB_WARN = 13, // call log_warning on black boxed module
SB_EXCL_BB_ERR = 14, // call log_error on black boxed module
SB_EXCL_BB_CMDERR = 15 // call log_cmd_error on black boxed module
};
struct Const;
struct AttrObject;
struct NamedObject;
struct Selection;
struct Monitor;
struct Design;
@ -869,6 +894,11 @@ struct RTLIL::AttrObject
vector<int> get_intvec_attribute(const RTLIL::IdString &id) const;
};
struct RTLIL::NamedObject : public RTLIL::AttrObject
{
RTLIL::IdString name;
};
struct RTLIL::SigChunk
{
RTLIL::Wire *wire;
@ -1134,32 +1164,94 @@ public:
struct RTLIL::Selection
{
// selection includes boxed modules
bool selects_boxes;
// selection covers full design, including boxed modules
bool complete_selection;
// selection covers full design, not including boxed modules
bool full_selection;
pool<RTLIL::IdString> selected_modules;
dict<RTLIL::IdString, pool<RTLIL::IdString>> selected_members;
RTLIL::Design *current_design;
Selection(bool full = true) : full_selection(full) { }
// create a new selection
Selection(
// should the selection cover the full design
bool full = true,
// should the selection include boxed modules
bool boxes = false,
// the design to select from
RTLIL::Design *design = nullptr
) :
full_selection(full && !boxes), selects_boxes(boxes), complete_selection(full && boxes), current_design(design) { }
// checks if the given module exists in the current design and is a
// boxed module, warning the user if the current design is not set
bool boxed_module(const RTLIL::IdString &mod_name) const;
// checks if the given module is included in this selection
bool selected_module(const RTLIL::IdString &mod_name) const;
// checks if the given module is wholly included in this selection,
// i.e. not partially selected
bool selected_whole_module(const RTLIL::IdString &mod_name) const;
// checks if the given member from the given module is included in this
// selection
bool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;
// optimizes this selection for the given design by:
// - removing non-existent modules and members, any boxed modules and
// their members (if selection does not include boxes), and any
// partially selected modules with no selected members;
// - marking partially selected modules as wholly selected if all
// members of that module are selected; and
// - marking selection as a complete_selection if all modules in the
// given design are selected, or a full_selection if it does not
// include boxes.
void optimize(RTLIL::Design *design);
// checks if selection covers full design (may or may not include
// boxed-modules)
bool selects_all() const {
return full_selection || complete_selection;
}
// add whole module to this selection
template<typename T1> void select(T1 *module) {
if (!full_selection && selected_modules.count(module->name) == 0) {
if (!selects_all() && selected_modules.count(module->name) == 0) {
selected_modules.insert(module->name);
selected_members.erase(module->name);
if (module->get_blackbox_attribute())
selects_boxes = true;
}
}
// add member of module to this selection
template<typename T1, typename T2> void select(T1 *module, T2 *member) {
if (!full_selection && selected_modules.count(module->name) == 0)
if (!selects_all() && selected_modules.count(module->name) == 0) {
selected_members[module->name].insert(member->name);
if (module->get_blackbox_attribute())
selects_boxes = true;
}
}
// checks if selection is empty
bool empty() const {
return !full_selection && selected_modules.empty() && selected_members.empty();
return !selects_all() && selected_modules.empty() && selected_members.empty();
}
// clear this selection, leaving it empty
void clear();
// create a new selection which is empty
static Selection EmptySelection(RTLIL::Design *design = nullptr) { return Selection(false, false, design); };
// create a new selection with all non-boxed modules
static Selection FullSelection(RTLIL::Design *design = nullptr) { return Selection(true, false, design); };
// create a new selection with all modules, including boxes
static Selection CompleteSelection(RTLIL::Design *design = nullptr) { return Selection(true, true, design); };
};
struct RTLIL::Monitor
@ -1213,7 +1305,7 @@ struct RTLIL::Design
RTLIL::ObjRange<RTLIL::Module*> modules();
RTLIL::Module *module(const RTLIL::IdString &name);
const RTLIL::Module *module(const RTLIL::IdString &name) const;
RTLIL::Module *top_module();
RTLIL::Module *top_module() const;
bool has(const RTLIL::IdString &id) const {
return modules_.count(id) != 0;
@ -1240,57 +1332,118 @@ struct RTLIL::Design
void check();
void optimize();
// checks if the given module is included in the current selection
bool selected_module(const RTLIL::IdString &mod_name) const;
// checks if the given module is wholly included in the current
// selection, i.e. not partially selected
bool selected_whole_module(const RTLIL::IdString &mod_name) const;
// checks if the given member from the given module is included in the
// current selection
bool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;
// checks if the given module is included in the current selection
bool selected_module(RTLIL::Module *mod) const;
// checks if the given module is wholly included in the current
// selection, i.e. not partially selected
bool selected_whole_module(RTLIL::Module *mod) const;
// push the given selection to the selection stack
void push_selection(RTLIL::Selection sel);
// push a new selection to the selection stack, with nothing selected
void push_empty_selection();
// push a new selection to the selection stack, with all non-boxed
// modules selected
void push_full_selection();
// push a new selection to the selection stack, with all modules
// selected including boxes
void push_complete_selection();
// pop the current selection from the stack, returning to a full
// selection (no boxes) if the stack is empty
void pop_selection();
// get the current selection
RTLIL::Selection &selection() {
return selection_stack.back();
}
// get the current selection
const RTLIL::Selection &selection() const {
return selection_stack.back();
}
// is the current selection a full selection (no boxes)
bool full_selection() const {
return selection_stack.back().full_selection;
return selection().full_selection;
}
// is the given module in the current selection
template<typename T1> bool selected(T1 *module) const {
return selected_module(module->name);
}
// is the given member of the given module in the current selection
template<typename T1, typename T2> bool selected(T1 *module, T2 *member) const {
return selected_member(module->name, member->name);
}
// add whole module to the current selection
template<typename T1> void select(T1 *module) {
if (selection_stack.size() > 0) {
RTLIL::Selection &sel = selection_stack.back();
sel.select(module);
}
RTLIL::Selection &sel = selection();
sel.select(module);
}
// add member of module to the current selection
template<typename T1, typename T2> void select(T1 *module, T2 *member) {
if (selection_stack.size() > 0) {
RTLIL::Selection &sel = selection_stack.back();
sel.select(module, member);
}
RTLIL::Selection &sel = selection();
sel.select(module, member);
}
std::vector<RTLIL::Module*> selected_modules() const;
std::vector<RTLIL::Module*> selected_whole_modules() const;
std::vector<RTLIL::Module*> selected_whole_modules_warn(bool include_wb = false) const;
// returns all selected modules
std::vector<RTLIL::Module*> selected_modules(
// controls if partially selected modules are included
RTLIL::SelectPartials partials = SELECT_ALL,
// controls if boxed modules are included
RTLIL::SelectBoxes boxes = SB_UNBOXED_WARN
) const;
// returns all selected modules, and may include boxes
std::vector<RTLIL::Module*> all_selected_modules() const { return selected_modules(SELECT_ALL, SB_ALL); }
// returns all selected unboxed modules, silently ignoring any boxed
// modules in the selection
std::vector<RTLIL::Module*> selected_unboxed_modules() const { return selected_modules(SELECT_ALL, SB_UNBOXED_ONLY); }
// returns all selected unboxed modules, warning the user if any boxed
// modules have been ignored
std::vector<RTLIL::Module*> selected_unboxed_modules_warn() const { return selected_modules(SELECT_ALL, SB_UNBOXED_WARN); }
[[deprecated("Use select_unboxed_whole_modules() to maintain prior behaviour, or consider one of the other selected whole module helpers.")]]
std::vector<RTLIL::Module*> selected_whole_modules() const { return selected_modules(SELECT_WHOLE_ONLY, SB_UNBOXED_WARN); }
// returns all selected whole modules, silently ignoring partially
// selected modules, and may include boxes
std::vector<RTLIL::Module*> all_selected_whole_modules() const { return selected_modules(SELECT_WHOLE_ONLY, SB_ALL); }
// returns all selected whole modules, warning the user if any partially
// selected or boxed modules have been ignored; optionally includes
// selected whole modules with the 'whitebox' attribute
std::vector<RTLIL::Module*> selected_whole_modules_warn(
// should whole modules with the 'whitebox' attribute be
// included
bool include_wb = false
) const { return selected_modules(SELECT_WHOLE_WARN, include_wb ? SB_EXCL_BB_WARN : SB_UNBOXED_WARN); }
// returns all selected unboxed whole modules, silently ignoring
// partially selected or boxed modules
std::vector<RTLIL::Module*> selected_unboxed_whole_modules() const { return selected_modules(SELECT_WHOLE_ONLY, SB_UNBOXED_ONLY); }
// returns all selected unboxed whole modules, warning the user if any
// partially selected or boxed modules have been ignored
std::vector<RTLIL::Module*> selected_unboxed_whole_modules_warn() const { return selected_modules(SELECT_WHOLE_WARN, SB_UNBOXED_WARN); }
#ifdef WITH_PYTHON
static std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);
#endif
};
struct RTLIL::Module : public RTLIL::AttrObject
struct RTLIL::Module : public RTLIL::NamedObject
{
Hasher::hash_t hashidx_;
[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }
@ -1313,7 +1466,6 @@ public:
std::vector<RTLIL::SigSig> connections_;
std::vector<RTLIL::Binding*> bindings_;
RTLIL::IdString name;
idict<RTLIL::IdString> avail_parameters;
dict<RTLIL::IdString, RTLIL::Const> parameter_default_values;
dict<RTLIL::IdString, RTLIL::Memory*> memories;
@ -1358,8 +1510,14 @@ public:
bool has_memories_warn() const;
bool has_processes_warn() const;
bool is_selected() const;
bool is_selected_whole() const;
std::vector<RTLIL::Wire*> selected_wires() const;
std::vector<RTLIL::Cell*> selected_cells() const;
std::vector<RTLIL::Memory*> selected_memories() const;
std::vector<RTLIL::Process*> selected_processes() const;
std::vector<RTLIL::NamedObject*> selected_members() const;
template<typename T> bool selected(T *member) const {
return design->selected_member(name, member->name);
@ -1645,7 +1803,7 @@ namespace RTLIL_BACKEND {
void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);
}
struct RTLIL::Wire : public RTLIL::AttrObject
struct RTLIL::Wire : public RTLIL::NamedObject
{
Hasher::hash_t hashidx_;
[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }
@ -1668,7 +1826,6 @@ public:
void operator=(RTLIL::Wire &other) = delete;
RTLIL::Module *module;
RTLIL::IdString name;
int width, start_offset, port_id;
bool port_input, port_output, upto, is_signed;
@ -1697,14 +1854,13 @@ inline int GetSize(RTLIL::Wire *wire) {
return wire->width;
}
struct RTLIL::Memory : public RTLIL::AttrObject
struct RTLIL::Memory : public RTLIL::NamedObject
{
Hasher::hash_t hashidx_;
[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }
Memory();
RTLIL::IdString name;
int width, start_offset, size;
#ifdef WITH_PYTHON
~Memory();
@ -1712,7 +1868,7 @@ struct RTLIL::Memory : public RTLIL::AttrObject
#endif
};
struct RTLIL::Cell : public RTLIL::AttrObject
struct RTLIL::Cell : public RTLIL::NamedObject
{
Hasher::hash_t hashidx_;
[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }
@ -1729,7 +1885,6 @@ public:
void operator=(RTLIL::Cell &other) = delete;
RTLIL::Module *module;
RTLIL::IdString name;
RTLIL::IdString type;
dict<RTLIL::IdString, RTLIL::SigSpec> connections_;
dict<RTLIL::IdString, RTLIL::Const> parameters;
@ -1822,7 +1977,7 @@ struct RTLIL::SyncRule
RTLIL::SyncRule *clone() const;
};
struct RTLIL::Process : public RTLIL::AttrObject
struct RTLIL::Process : public RTLIL::NamedObject
{
Hasher::hash_t hashidx_;
[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }
@ -1834,7 +1989,6 @@ protected:
~Process();
public:
RTLIL::IdString name;
RTLIL::Module *module;
RTLIL::CaseRule root_case;
std::vector<RTLIL::SyncRule*> syncs;