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Reinstate #4768

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Revert the reversion so that we can fix the bugs that the PR missed.
This commit is contained in:
Krystine Sherwin 2025-04-08 11:57:43 +12:00
parent bf386feba7
commit cd3b914132
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38 changed files with 700 additions and 263 deletions
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2
kernel/driver.cc
View file

@ -111,7 +111,7 @@ void run(const char *command)
log_last_error = "";
} catch (...) {
while (GetSize(yosys_get_design()->selection_stack) > selSize)
yosys_get_design()->selection_stack.pop_back();
yosys_get_design()->pop_selection();
throw;
}
}

24
kernel/register.cc
View file

@ -260,18 +260,18 @@ void Pass::call(RTLIL::Design *design, std::vector<std::string> args)
pass_register[args[0]]->execute(args, design);
pass_register[args[0]]->post_execute(state);
while (design->selection_stack.size() > orig_sel_stack_pos)
design->selection_stack.pop_back();
design->pop_selection();
}
void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::string command)
{
std::string backup_selected_active_module = design->selected_active_module;
design->selected_active_module.clear();
design->selection_stack.push_back(selection);
design->push_selection(selection);
Pass::call(design, command);
design->selection_stack.pop_back();
design->pop_selection();
design->selected_active_module = backup_selected_active_module;
}
@ -279,11 +279,11 @@ void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &sele
{
std::string backup_selected_active_module = design->selected_active_module;
design->selected_active_module.clear();
design->selection_stack.push_back(selection);
design->push_selection(selection);
Pass::call(design, args);
design->selection_stack.pop_back();
design->pop_selection();
design->selected_active_module = backup_selected_active_module;
}
@ -291,12 +291,12 @@ void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::str
{
std::string backup_selected_active_module = design->selected_active_module;
design->selected_active_module = module->name.str();
design->selection_stack.push_back(RTLIL::Selection(false));
design->selection_stack.back().select(module);
design->push_empty_selection();
design->select(module);
Pass::call(design, command);
design->selection_stack.pop_back();
design->pop_selection();
design->selected_active_module = backup_selected_active_module;
}
@ -304,12 +304,12 @@ void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vec
{
std::string backup_selected_active_module = design->selected_active_module;
design->selected_active_module = module->name.str();
design->selection_stack.push_back(RTLIL::Selection(false));
design->selection_stack.back().select(module);
design->push_empty_selection();
design->select(module);
Pass::call(design, args);
design->selection_stack.pop_back();
design->pop_selection();
design->selected_active_module = backup_selected_active_module;
}
@ -651,7 +651,7 @@ void Backend::backend_call(RTLIL::Design *design, std::ostream *f, std::string f
}
while (design->selection_stack.size() > orig_sel_stack_pos)
design->selection_stack.pop_back();
design->pop_selection();
}
struct SimHelper {

219
kernel/rtlil.cc
View file

@ -766,8 +766,23 @@ vector<int> RTLIL::AttrObject::get_intvec_attribute(const RTLIL::IdString &id) c
return data;
}
bool RTLIL::Selection::boxed_module(const RTLIL::IdString &mod_name) const
{
if (current_design != nullptr) {
auto module = current_design->module(mod_name);
return module && module->get_blackbox_attribute();
} else {
log_warning("Unable to check if module is boxed for null design.\n");
return false;
}
}
bool RTLIL::Selection::selected_module(const RTLIL::IdString &mod_name) const
{
if (complete_selection)
return true;
if (!selects_boxes && boxed_module(mod_name))
return false;
if (full_selection)
return true;
if (selected_modules.count(mod_name) > 0)
@ -779,6 +794,10 @@ bool RTLIL::Selection::selected_module(const RTLIL::IdString &mod_name) const
bool RTLIL::Selection::selected_whole_module(const RTLIL::IdString &mod_name) const
{
if (complete_selection)
return true;
if (!selects_boxes && boxed_module(mod_name))
return false;
if (full_selection)
return true;
if (selected_modules.count(mod_name) > 0)
@ -788,6 +807,10 @@ bool RTLIL::Selection::selected_whole_module(const RTLIL::IdString &mod_name) co
bool RTLIL::Selection::selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const
{
if (complete_selection)
return true;
if (!selects_boxes && boxed_module(mod_name))
return false;
if (full_selection)
return true;
if (selected_modules.count(mod_name) > 0)
@ -800,7 +823,17 @@ bool RTLIL::Selection::selected_member(const RTLIL::IdString &mod_name, const RT
void RTLIL::Selection::optimize(RTLIL::Design *design)
{
if (full_selection) {
if (design != current_design) {
current_design = design;
}
if (selects_boxes && full_selection)
complete_selection = true;
if (complete_selection) {
full_selection = false;
selects_boxes = true;
}
if (selects_all()) {
selected_modules.clear();
selected_members.clear();
return;
@ -810,7 +843,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design)
del_list.clear();
for (auto mod_name : selected_modules) {
if (design->modules_.count(mod_name) == 0)
if (current_design->modules_.count(mod_name) == 0 || (!selects_boxes && boxed_module(mod_name)))
del_list.push_back(mod_name);
selected_members.erase(mod_name);
}
@ -819,7 +852,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design)
del_list.clear();
for (auto &it : selected_members)
if (design->modules_.count(it.first) == 0)
if (current_design->modules_.count(it.first) == 0 || (!selects_boxes && boxed_module(it.first)))
del_list.push_back(it.first);
for (auto mod_name : del_list)
selected_members.erase(mod_name);
@ -827,7 +860,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design)
for (auto &it : selected_members) {
del_list.clear();
for (auto memb_name : it.second)
if (design->modules_[it.first]->count_id(memb_name) == 0)
if (current_design->modules_[it.first]->count_id(memb_name) == 0)
del_list.push_back(memb_name);
for (auto memb_name : del_list)
it.second.erase(memb_name);
@ -838,8 +871,8 @@ void RTLIL::Selection::optimize(RTLIL::Design *design)
for (auto &it : selected_members)
if (it.second.size() == 0)
del_list.push_back(it.first);
else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
else if (it.second.size() == current_design->modules_[it.first]->wires_.size() + current_design->modules_[it.first]->memories.size() +
current_design->modules_[it.first]->cells_.size() + current_design->modules_[it.first]->processes.size())
add_list.push_back(it.first);
for (auto mod_name : del_list)
selected_members.erase(mod_name);
@ -848,13 +881,24 @@ void RTLIL::Selection::optimize(RTLIL::Design *design)
selected_modules.insert(mod_name);
}
if (selected_modules.size() == design->modules_.size()) {
full_selection = true;
if (selected_modules.size() == current_design->modules_.size()) {
selected_modules.clear();
selected_members.clear();
if (selects_boxes)
complete_selection = true;
else
full_selection = true;
}
}
void RTLIL::Selection::clear()
{
full_selection = false;
complete_selection = false;
selected_modules.clear();
selected_members.clear();
}
RTLIL::Design::Design()
: verilog_defines (new define_map_t)
{
@ -863,7 +907,7 @@ RTLIL::Design::Design()
hashidx_ = hashidx_count;
refcount_modules_ = 0;
selection_stack.push_back(RTLIL::Selection());
push_full_selection();
#ifdef WITH_PYTHON
RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
@ -908,7 +952,7 @@ const RTLIL::Module *RTLIL::Design::module(const RTLIL::IdString& name) const
return modules_.count(name) ? modules_.at(name) : NULL;
}
RTLIL::Module *RTLIL::Design::top_module()
RTLIL::Module *RTLIL::Design::top_module() const
{
RTLIL::Module *module = nullptr;
int module_count = 0;
@ -1066,6 +1110,7 @@ void RTLIL::Design::sort()
void RTLIL::Design::check()
{
#ifndef NDEBUG
log_assert(!selection_stack.empty());
for (auto &it : modules_) {
log_assert(this == it.second->design);
log_assert(it.first == it.second->name);
@ -1089,27 +1134,21 @@ bool RTLIL::Design::selected_module(const RTLIL::IdString& mod_name) const
{
if (!selected_active_module.empty() && mod_name != selected_active_module)
return false;
if (selection_stack.size() == 0)
return true;
return selection_stack.back().selected_module(mod_name);
return selection().selected_module(mod_name);
}
bool RTLIL::Design::selected_whole_module(const RTLIL::IdString& mod_name) const
{
if (!selected_active_module.empty() && mod_name != selected_active_module)
return false;
if (selection_stack.size() == 0)
return true;
return selection_stack.back().selected_whole_module(mod_name);
return selection().selected_whole_module(mod_name);
}
bool RTLIL::Design::selected_member(const RTLIL::IdString& mod_name, const RTLIL::IdString& memb_name) const
{
if (!selected_active_module.empty() && mod_name != selected_active_module)
return false;
if (selection_stack.size() == 0)
return true;
return selection_stack.back().selected_member(mod_name, memb_name);
return selection().selected_member(mod_name, memb_name);
}
bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
@ -1122,37 +1161,86 @@ bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
return selected_whole_module(mod->name);
}
std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
void RTLIL::Design::push_selection(RTLIL::Selection sel)
{
std::vector<RTLIL::Module*> result;
result.reserve(modules_.size());
for (auto &it : modules_)
if (selected_module(it.first) && !it.second->get_blackbox_attribute())
result.push_back(it.second);
return result;
sel.current_design = this;
selection_stack.push_back(sel);
}
std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
void RTLIL::Design::push_empty_selection()
{
std::vector<RTLIL::Module*> result;
result.reserve(modules_.size());
for (auto &it : modules_)
if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
result.push_back(it.second);
return result;
push_selection(RTLIL::Selection::EmptySelection(this));
}
std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn(bool include_wb) const
void RTLIL::Design::push_full_selection()
{
push_selection(RTLIL::Selection::FullSelection(this));
}
void RTLIL::Design::push_complete_selection()
{
push_selection(RTLIL::Selection::CompleteSelection(this));
}
void RTLIL::Design::pop_selection()
{
selection_stack.pop_back();
// Default to a full_selection if we ran out of stack
if (selection_stack.empty())
push_full_selection();
}
std::vector<RTLIL::Module*> RTLIL::Design::selected_modules(RTLIL::SelectPartials partials, RTLIL::SelectBoxes boxes) const
{
bool include_partials = partials == RTLIL::SELECT_ALL;
bool exclude_boxes = (partials & RTLIL::SB_UNBOXED_ONLY) != 0;
bool ignore_wb = (partials & RTLIL::SB_INCL_WB) != 0;
std::vector<RTLIL::Module*> result;
result.reserve(modules_.size());
for (auto &it : modules_)
if (it.second->get_blackbox_attribute(include_wb))
continue;
else if (selected_whole_module(it.first))
result.push_back(it.second);
else if (selected_module(it.first))
log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
if (selected_whole_module(it.first) || (include_partials && selected_module(it.first))) {
if (!(exclude_boxes && it.second->get_blackbox_attribute(ignore_wb)))
result.push_back(it.second);
else
switch (boxes)
{
case RTLIL::SB_UNBOXED_WARN:
log_warning("Ignoring boxed module %s.\n", log_id(it.first));
break;
case RTLIL::SB_EXCL_BB_WARN:
log_warning("Ignoring blackbox module %s.\n", log_id(it.first));
break;
case RTLIL::SB_UNBOXED_ERR:
log_error("Unsupported boxed module %s.\n", log_id(it.first));
break;
case RTLIL::SB_EXCL_BB_ERR:
log_error("Unsupported blackbox module %s.\n", log_id(it.first));
break;
case RTLIL::SB_UNBOXED_CMDERR:
log_cmd_error("Unsupported boxed module %s.\n", log_id(it.first));
break;
case RTLIL::SB_EXCL_BB_CMDERR:
log_cmd_error("Unsupported blackbox module %s.\n", log_id(it.first));
break;
default:
break;
}
} else if (!include_partials && selected_module(it.first)) {
switch(partials)
{
case RTLIL::SELECT_WHOLE_WARN:
log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
break;
case RTLIL::SELECT_WHOLE_ERR:
log_error("Unsupported partially selected module %s.\n", log_id(it.first));
break;
case RTLIL::SELECT_WHOLE_CMDERR:
log_cmd_error("Unsupported partially selected module %s.\n", log_id(it.first));
break;
default:
break;
}
}
return result;
}
@ -2284,6 +2372,13 @@ void RTLIL::Module::check()
log_assert(!packed_memids.count(memid));
packed_memids.insert(memid);
}
auto cell_mod = design->module(it.first);
if (cell_mod != nullptr) {
// assertion check below to make sure that there are no
// cases where a cell has a blackbox attribute since
// that is deprecated
log_assert(!it.second->get_blackbox_attribute());
}
}
for (auto &it : processes) {
@ -2411,6 +2506,16 @@ bool RTLIL::Module::has_processes_warn() const
return !processes.empty();
}
bool RTLIL::Module::is_selected() const
{
return design->selected_module(this->name);
}
bool RTLIL::Module::is_selected_whole() const
{
return design->selected_whole_module(this->name);
}
std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
{
std::vector<RTLIL::Wire*> result;
@ -2431,6 +2536,40 @@ std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
return result;
}
std::vector<RTLIL::Memory*> RTLIL::Module::selected_memories() const
{
std::vector<RTLIL::Memory*> result;
result.reserve(memories.size());
for (auto &it : memories)
if (design->selected(this, it.second))
result.push_back(it.second);
return result;
}
std::vector<RTLIL::Process*> RTLIL::Module::selected_processes() const
{
std::vector<RTLIL::Process*> result;
result.reserve(processes.size());
for (auto &it : processes)
if (design->selected(this, it.second))
result.push_back(it.second);
return result;
}
std::vector<RTLIL::NamedObject*> RTLIL::Module::selected_members() const
{
std::vector<RTLIL::NamedObject*> result;
auto cells = selected_cells();
auto memories = selected_memories();
auto wires = selected_wires();
auto processes = selected_processes();
result.insert(result.end(), cells.begin(), cells.end());
result.insert(result.end(), memories.begin(), memories.end());
result.insert(result.end(), wires.begin(), wires.end());
result.insert(result.end(), processes.begin(), processes.end());
return result;
}
void RTLIL::Module::add(RTLIL::Wire *wire)
{
log_assert(!wire->name.empty());

208
kernel/rtlil.h
View file

@ -56,8 +56,33 @@ namespace RTLIL
CONST_FLAG_REAL = 4 // only used for parameters
};
enum SelectPartials : unsigned char {
SELECT_ALL = 0, // include partial modules
SELECT_WHOLE_ONLY = 1, // ignore partial modules
SELECT_WHOLE_WARN = 2, // call log_warning on partial module
SELECT_WHOLE_ERR = 3, // call log_error on partial module
SELECT_WHOLE_CMDERR = 4 // call log_cmd_error on partial module
};
enum SelectBoxes : unsigned char {
SB_ALL = 0, // include boxed modules
SB_WARN = 1, // helper for log_warning
SB_ERR = 2, // helper for log_error
SB_CMDERR = 3, // helper for log_cmd_error
SB_UNBOXED_ONLY = 4, // ignore boxed modules
SB_UNBOXED_WARN = 5, // call log_warning on boxed module
SB_UNBOXED_ERR = 6, // call log_error on boxed module
SB_UNBOXED_CMDERR = 7, // call log_cmd_error on boxed module
SB_INCL_WB = 8, // helper for white boxes
SB_EXCL_BB_ONLY = 12, // ignore black boxes, but not white boxes
SB_EXCL_BB_WARN = 13, // call log_warning on black boxed module
SB_EXCL_BB_ERR = 14, // call log_error on black boxed module
SB_EXCL_BB_CMDERR = 15 // call log_cmd_error on black boxed module
};
struct Const;
struct AttrObject;
struct NamedObject;
struct Selection;
struct Monitor;
struct Design;
@ -869,6 +894,11 @@ struct RTLIL::AttrObject
vector<int> get_intvec_attribute(const RTLIL::IdString &id) const;
};
struct RTLIL::NamedObject : public RTLIL::AttrObject
{
RTLIL::IdString name;
};
struct RTLIL::SigChunk
{
RTLIL::Wire *wire;
@ -1134,32 +1164,94 @@ public:
struct RTLIL::Selection
{
// selection includes boxed modules
bool selects_boxes;
// selection covers full design, including boxed modules
bool complete_selection;
// selection covers full design, not including boxed modules
bool full_selection;
pool<RTLIL::IdString> selected_modules;
dict<RTLIL::IdString, pool<RTLIL::IdString>> selected_members;
RTLIL::Design *current_design;
Selection(bool full = true) : full_selection(full) { }
// create a new selection
Selection(
// should the selection cover the full design
bool full = true,
// should the selection include boxed modules
bool boxes = false,
// the design to select from
RTLIL::Design *design = nullptr
) :
full_selection(full && !boxes), selects_boxes(boxes), complete_selection(full && boxes), current_design(design) { }
// checks if the given module exists in the current design and is a
// boxed module, warning the user if the current design is not set
bool boxed_module(const RTLIL::IdString &mod_name) const;
// checks if the given module is included in this selection
bool selected_module(const RTLIL::IdString &mod_name) const;
// checks if the given module is wholly included in this selection,
// i.e. not partially selected
bool selected_whole_module(const RTLIL::IdString &mod_name) const;
// checks if the given member from the given module is included in this
// selection
bool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;
// optimizes this selection for the given design by:
// - removing non-existent modules and members, any boxed modules and
// their members (if selection does not include boxes), and any
// partially selected modules with no selected members;
// - marking partially selected modules as wholly selected if all
// members of that module are selected; and
// - marking selection as a complete_selection if all modules in the
// given design are selected, or a full_selection if it does not
// include boxes.
void optimize(RTLIL::Design *design);
// checks if selection covers full design (may or may not include
// boxed-modules)
bool selects_all() const {
return full_selection || complete_selection;
}
// add whole module to this selection
template<typename T1> void select(T1 *module) {
if (!full_selection && selected_modules.count(module->name) == 0) {
if (!selects_all() && selected_modules.count(module->name) == 0) {
selected_modules.insert(module->name);
selected_members.erase(module->name);
if (module->get_blackbox_attribute())
selects_boxes = true;
}
}
// add member of module to this selection
template<typename T1, typename T2> void select(T1 *module, T2 *member) {
if (!full_selection && selected_modules.count(module->name) == 0)
if (!selects_all() && selected_modules.count(module->name) == 0) {
selected_members[module->name].insert(member->name);
if (module->get_blackbox_attribute())
selects_boxes = true;
}
}
// checks if selection is empty
bool empty() const {
return !full_selection && selected_modules.empty() && selected_members.empty();
return !selects_all() && selected_modules.empty() && selected_members.empty();
}
// clear this selection, leaving it empty
void clear();
// create a new selection which is empty
static Selection EmptySelection(RTLIL::Design *design = nullptr) { return Selection(false, false, design); };
// create a new selection with all non-boxed modules
static Selection FullSelection(RTLIL::Design *design = nullptr) { return Selection(true, false, design); };
// create a new selection with all modules, including boxes
static Selection CompleteSelection(RTLIL::Design *design = nullptr) { return Selection(true, true, design); };
};
struct RTLIL::Monitor
@ -1213,7 +1305,7 @@ struct RTLIL::Design
RTLIL::ObjRange<RTLIL::Module*> modules();
RTLIL::Module *module(const RTLIL::IdString &name);
const RTLIL::Module *module(const RTLIL::IdString &name) const;
RTLIL::Module *top_module();
RTLIL::Module *top_module() const;
bool has(const RTLIL::IdString &id) const {
return modules_.count(id) != 0;
@ -1240,57 +1332,118 @@ struct RTLIL::Design
void check();
void optimize();
// checks if the given module is included in the current selection
bool selected_module(const RTLIL::IdString &mod_name) const;
// checks if the given module is wholly included in the current
// selection, i.e. not partially selected
bool selected_whole_module(const RTLIL::IdString &mod_name) const;
// checks if the given member from the given module is included in the
// current selection
bool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;
// checks if the given module is included in the current selection
bool selected_module(RTLIL::Module *mod) const;
// checks if the given module is wholly included in the current
// selection, i.e. not partially selected
bool selected_whole_module(RTLIL::Module *mod) const;
// push the given selection to the selection stack
void push_selection(RTLIL::Selection sel);
// push a new selection to the selection stack, with nothing selected
void push_empty_selection();
// push a new selection to the selection stack, with all non-boxed
// modules selected
void push_full_selection();
// push a new selection to the selection stack, with all modules
// selected including boxes
void push_complete_selection();
// pop the current selection from the stack, returning to a full
// selection (no boxes) if the stack is empty
void pop_selection();
// get the current selection
RTLIL::Selection &selection() {
return selection_stack.back();
}
// get the current selection
const RTLIL::Selection &selection() const {
return selection_stack.back();
}
// is the current selection a full selection (no boxes)
bool full_selection() const {
return selection_stack.back().full_selection;
return selection().full_selection;
}
// is the given module in the current selection
template<typename T1> bool selected(T1 *module) const {
return selected_module(module->name);
}
// is the given member of the given module in the current selection
template<typename T1, typename T2> bool selected(T1 *module, T2 *member) const {
return selected_member(module->name, member->name);
}
// add whole module to the current selection
template<typename T1> void select(T1 *module) {
if (selection_stack.size() > 0) {
RTLIL::Selection &sel = selection_stack.back();
sel.select(module);
}
RTLIL::Selection &sel = selection();
sel.select(module);
}
// add member of module to the current selection
template<typename T1, typename T2> void select(T1 *module, T2 *member) {
if (selection_stack.size() > 0) {
RTLIL::Selection &sel = selection_stack.back();
sel.select(module, member);
}
RTLIL::Selection &sel = selection();
sel.select(module, member);
}
std::vector<RTLIL::Module*> selected_modules() const;
std::vector<RTLIL::Module*> selected_whole_modules() const;
std::vector<RTLIL::Module*> selected_whole_modules_warn(bool include_wb = false) const;
// returns all selected modules
std::vector<RTLIL::Module*> selected_modules(
// controls if partially selected modules are included
RTLIL::SelectPartials partials = SELECT_ALL,
// controls if boxed modules are included
RTLIL::SelectBoxes boxes = SB_UNBOXED_WARN
) const;
// returns all selected modules, and may include boxes
std::vector<RTLIL::Module*> all_selected_modules() const { return selected_modules(SELECT_ALL, SB_ALL); }
// returns all selected unboxed modules, silently ignoring any boxed
// modules in the selection
std::vector<RTLIL::Module*> selected_unboxed_modules() const { return selected_modules(SELECT_ALL, SB_UNBOXED_ONLY); }
// returns all selected unboxed modules, warning the user if any boxed
// modules have been ignored
std::vector<RTLIL::Module*> selected_unboxed_modules_warn() const { return selected_modules(SELECT_ALL, SB_UNBOXED_WARN); }
[[deprecated("Use select_unboxed_whole_modules() to maintain prior behaviour, or consider one of the other selected whole module helpers.")]]
std::vector<RTLIL::Module*> selected_whole_modules() const { return selected_modules(SELECT_WHOLE_ONLY, SB_UNBOXED_WARN); }
// returns all selected whole modules, silently ignoring partially
// selected modules, and may include boxes
std::vector<RTLIL::Module*> all_selected_whole_modules() const { return selected_modules(SELECT_WHOLE_ONLY, SB_ALL); }
// returns all selected whole modules, warning the user if any partially
// selected or boxed modules have been ignored; optionally includes
// selected whole modules with the 'whitebox' attribute
std::vector<RTLIL::Module*> selected_whole_modules_warn(
// should whole modules with the 'whitebox' attribute be
// included
bool include_wb = false
) const { return selected_modules(SELECT_WHOLE_WARN, include_wb ? SB_EXCL_BB_WARN : SB_UNBOXED_WARN); }
// returns all selected unboxed whole modules, silently ignoring
// partially selected or boxed modules
std::vector<RTLIL::Module*> selected_unboxed_whole_modules() const { return selected_modules(SELECT_WHOLE_ONLY, SB_UNBOXED_ONLY); }
// returns all selected unboxed whole modules, warning the user if any
// partially selected or boxed modules have been ignored
std::vector<RTLIL::Module*> selected_unboxed_whole_modules_warn() const { return selected_modules(SELECT_WHOLE_WARN, SB_UNBOXED_WARN); }
#ifdef WITH_PYTHON
static std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);
#endif
};
struct RTLIL::Module : public RTLIL::AttrObject
struct RTLIL::Module : public RTLIL::NamedObject
{
Hasher::hash_t hashidx_;
[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }
@ -1313,7 +1466,6 @@ public:
std::vector<RTLIL::SigSig> connections_;
std::vector<RTLIL::Binding*> bindings_;
RTLIL::IdString name;
idict<RTLIL::IdString> avail_parameters;
dict<RTLIL::IdString, RTLIL::Const> parameter_default_values;
dict<RTLIL::IdString, RTLIL::Memory*> memories;
@ -1358,8 +1510,14 @@ public:
bool has_memories_warn() const;
bool has_processes_warn() const;
bool is_selected() const;
bool is_selected_whole() const;
std::vector<RTLIL::Wire*> selected_wires() const;
std::vector<RTLIL::Cell*> selected_cells() const;
std::vector<RTLIL::Memory*> selected_memories() const;
std::vector<RTLIL::Process*> selected_processes() const;
std::vector<RTLIL::NamedObject*> selected_members() const;
template<typename T> bool selected(T *member) const {
return design->selected_member(name, member->name);
@ -1645,7 +1803,7 @@ namespace RTLIL_BACKEND {
void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);
}
struct RTLIL::Wire : public RTLIL::AttrObject
struct RTLIL::Wire : public RTLIL::NamedObject
{
Hasher::hash_t hashidx_;
[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }
@ -1668,7 +1826,6 @@ public:
void operator=(RTLIL::Wire &other) = delete;
RTLIL::Module *module;
RTLIL::IdString name;
int width, start_offset, port_id;
bool port_input, port_output, upto, is_signed;
@ -1697,14 +1854,13 @@ inline int GetSize(RTLIL::Wire *wire) {
return wire->width;
}
struct RTLIL::Memory : public RTLIL::AttrObject
struct RTLIL::Memory : public RTLIL::NamedObject
{
Hasher::hash_t hashidx_;
[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }
Memory();
RTLIL::IdString name;
int width, start_offset, size;
#ifdef WITH_PYTHON
~Memory();
@ -1712,7 +1868,7 @@ struct RTLIL::Memory : public RTLIL::AttrObject
#endif
};
struct RTLIL::Cell : public RTLIL::AttrObject
struct RTLIL::Cell : public RTLIL::NamedObject
{
Hasher::hash_t hashidx_;
[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }
@ -1729,7 +1885,6 @@ public:
void operator=(RTLIL::Cell &other) = delete;
RTLIL::Module *module;
RTLIL::IdString name;
RTLIL::IdString type;
dict<RTLIL::IdString, RTLIL::SigSpec> connections_;
dict<RTLIL::IdString, RTLIL::Const> parameters;
@ -1822,7 +1977,7 @@ struct RTLIL::SyncRule
RTLIL::SyncRule *clone() const;
};
struct RTLIL::Process : public RTLIL::AttrObject
struct RTLIL::Process : public RTLIL::NamedObject
{
Hasher::hash_t hashidx_;
[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }
@ -1834,7 +1989,6 @@ protected:
~Process();
public:
RTLIL::IdString name;
RTLIL::Module *module;
RTLIL::CaseRule root_case;
std::vector<RTLIL::SyncRule*> syncs;

2
kernel/tclapi.cc
View file

@ -114,7 +114,7 @@ static int tcl_yosys_cmd(ClientData, Tcl_Interp *interp, int argc, const char *a
if (in_repl) {
auto design = yosys_get_design();
while (design->selection_stack.size() > 1)
design->selection_stack.pop_back();
design->pop_selection();
log_reset_stack();
}
Tcl_SetResult(interp, (char *)"Yosys command produced an error", TCL_STATIC);

8
kernel/yosys.cc
View file

@ -312,11 +312,11 @@ const char *create_prompt(RTLIL::Design *design, int recursion_counter)
str += "yosys";
if (!design->selected_active_module.empty())
str += stringf(" [%s]", RTLIL::unescape_id(design->selected_active_module).c_str());
if (!design->selection_stack.empty() && !design->selection_stack.back().full_selection) {
if (!design->full_selection()) {
if (design->selected_active_module.empty())
str += "*";
else if (design->selection_stack.back().selected_modules.size() != 1 || design->selection_stack.back().selected_members.size() != 0 ||
design->selection_stack.back().selected_modules.count(design->selected_active_module) == 0)
else if (design->selection().selected_modules.size() != 1 || design->selection().selected_members.size() != 0 ||
design->selection().selected_modules.count(design->selected_active_module) == 0)
str += "*";
}
snprintf(buffer, 100, "%s> ", str.c_str());
@ -979,7 +979,7 @@ void shell(RTLIL::Design *design)
Pass::call(design, command);
} catch (log_cmd_error_exception) {
while (design->selection_stack.size() > 1)
design->selection_stack.pop_back();
design->pop_selection();
log_reset_stack();
}
design->check();