mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-09 07:33:25 +00:00
Reinstate #4768
Revert the reversion so that we can fix the bugs that the PR missed.
This commit is contained in:
parent
bf386feba7
commit
cd3b914132
38 changed files with 700 additions and 263 deletions
|
@ -304,8 +304,8 @@ void RTLIL_BACKEND::dump_conn(std::ostream &f, std::string indent, const RTLIL::
|
|||
|
||||
void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n)
|
||||
{
|
||||
bool print_header = flag_m || design->selected_whole_module(module->name);
|
||||
bool print_body = !flag_n || !design->selected_whole_module(module->name);
|
||||
bool print_header = flag_m || module->is_selected_whole();
|
||||
bool print_body = !flag_n || !module->is_selected_whole();
|
||||
|
||||
if (print_header)
|
||||
{
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue