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https://github.com/YosysHQ/yosys
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Improved xsthammer quartus support
This commit is contained in:
Clifford Wolf
parent
14c84c111b
commit
cd33db25d1
2 changed files with 484 additions and 1 deletions
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@ -84,3 +84,486 @@ assign obar = ~i;
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endmodule
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// ----------------------------------------------------------------------
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module cycloneiii_mac_data_reg (clk,
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data,
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ena,
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aclr,
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dataout
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);
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parameter data_width = 18;
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// INPUT PORTS
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input clk;
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input [17 : 0] data;
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input ena;
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input aclr;
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// OUTPUT PORTS
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output [17:0] dataout;
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// INTERNAL VARIABLES AND NETS
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reg clk_last_value;
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reg [17:0] dataout_tmp;
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wire [17:0] dataout_wire;
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// INTERNAL VARIABLES
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wire [17:0] data_ipd;
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wire enable;
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wire no_clr;
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reg d_viol;
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reg ena_viol;
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wire clk_ipd;
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wire ena_ipd;
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wire aclr_ipd;
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// BUFFER INPUTS
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buf (clk_ipd, clk);
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buf (ena_ipd, ena);
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buf (aclr_ipd, aclr);
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buf (data_ipd[0], data[0]);
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buf (data_ipd[1], data[1]);
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buf (data_ipd[2], data[2]);
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buf (data_ipd[3], data[3]);
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buf (data_ipd[4], data[4]);
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buf (data_ipd[5], data[5]);
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buf (data_ipd[6], data[6]);
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buf (data_ipd[7], data[7]);
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buf (data_ipd[8], data[8]);
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buf (data_ipd[9], data[9]);
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buf (data_ipd[10], data[10]);
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buf (data_ipd[11], data[11]);
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buf (data_ipd[12], data[12]);
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buf (data_ipd[13], data[13]);
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buf (data_ipd[14], data[14]);
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buf (data_ipd[15], data[15]);
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buf (data_ipd[16], data[16]);
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buf (data_ipd[17], data[17]);
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assign enable = (!aclr_ipd) && (ena_ipd);
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assign no_clr = (!aclr_ipd);
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initial
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begin
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clk_last_value <= 'b0;
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dataout_tmp <= 18'b0;
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end
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always @(clk_ipd or aclr_ipd)
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begin
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if (d_viol == 1'b1 || ena_viol == 1'b1)
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begin
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dataout_tmp <= 'bX;
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end
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else if (aclr_ipd == 1'b1)
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begin
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dataout_tmp <= 'b0;
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end
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else
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begin
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if ((clk_ipd === 1'b1) && (clk_last_value == 1'b0))
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if (ena_ipd === 1'b1)
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dataout_tmp <= data_ipd;
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end
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clk_last_value <= clk_ipd;
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end // always
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assign dataout_wire = dataout_tmp;
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and (dataout[0], dataout_wire[0], 1'b1);
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and (dataout[1], dataout_wire[1], 1'b1);
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and (dataout[2], dataout_wire[2], 1'b1);
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and (dataout[3], dataout_wire[3], 1'b1);
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and (dataout[4], dataout_wire[4], 1'b1);
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and (dataout[5], dataout_wire[5], 1'b1);
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and (dataout[6], dataout_wire[6], 1'b1);
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and (dataout[7], dataout_wire[7], 1'b1);
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and (dataout[8], dataout_wire[8], 1'b1);
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and (dataout[9], dataout_wire[9], 1'b1);
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and (dataout[10], dataout_wire[10], 1'b1);
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and (dataout[11], dataout_wire[11], 1'b1);
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and (dataout[12], dataout_wire[12], 1'b1);
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and (dataout[13], dataout_wire[13], 1'b1);
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and (dataout[14], dataout_wire[14], 1'b1);
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and (dataout[15], dataout_wire[15], 1'b1);
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and (dataout[16], dataout_wire[16], 1'b1);
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and (dataout[17], dataout_wire[17], 1'b1);
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endmodule //cycloneiii_mac_data_reg
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module cycloneiii_mac_sign_reg (
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clk,
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d,
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ena,
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aclr,
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q
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);
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// INPUT PORTS
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input clk;
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input d;
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input ena;
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input aclr;
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// OUTPUT PORTS
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output q;
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// INTERNAL VARIABLES
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reg clk_last_value;
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reg q_tmp;
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reg ena_viol;
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reg d_viol;
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wire enable;
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// DEFAULT VALUES THRO' PULLUPs
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// tri1 aclr, ena;
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wire d_ipd;
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wire clk_ipd;
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wire ena_ipd;
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wire aclr_ipd;
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buf (d_ipd, d);
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buf (clk_ipd, clk);
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buf (ena_ipd, ena);
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buf (aclr_ipd, aclr);
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assign enable = (!aclr_ipd) && (ena_ipd);
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initial
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begin
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clk_last_value <= 'b0;
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q_tmp <= 'b0;
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end
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always @ (clk_ipd or aclr_ipd)
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begin
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if (d_viol == 1'b1 || ena_viol == 1'b1)
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begin
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q_tmp <= 'bX;
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end
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else
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begin
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if (aclr_ipd == 1'b1)
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q_tmp <= 0;
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else if ((clk_ipd == 1'b1) && (clk_last_value == 1'b0))
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if (ena_ipd == 1'b1)
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q_tmp <= d_ipd;
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end
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clk_last_value <= clk_ipd;
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end
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and (q, q_tmp, 'b1);
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endmodule // cycloneiii_mac_sign_reg
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module cycloneiii_mac_mult_internal
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(
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dataa,
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datab,
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signa,
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signb,
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dataout
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);
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parameter dataa_width = 18;
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parameter datab_width = 18;
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parameter dataout_width = dataa_width + datab_width;
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// INPUT
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input [dataa_width-1:0] dataa;
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input [datab_width-1:0] datab;
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input signa;
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input signb;
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// OUTPUT
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output [dataout_width-1:0] dataout;
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// Internal variables
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wire [17:0] dataa_ipd;
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wire [17:0] datab_ipd;
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wire signa_ipd;
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wire signb_ipd;
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wire [dataout_width-1:0] dataout_tmp;
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wire ia_is_positive;
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wire ib_is_positive;
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wire [17:0] iabsa; // absolute value (i.e. positive) form of dataa input
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wire [17:0] iabsb; // absolute value (i.e. positive) form of datab input
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wire [35:0] iabsresult; // absolute value (i.e. positive) form of product (a * b)
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reg [17:0] i_ones; // padding with 1's for input negation
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// Input buffers
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buf (signa_ipd, signa);
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buf (signb_ipd, signb);
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// buf dataa_buf [dataa_width-1:0] (dataa_ipd[dataa_width-1:0], dataa);
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// buf datab_buf [datab_width-1:0] (datab_ipd[datab_width-1:0], datab);
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assign dataa_ipd[dataa_width-1:0] = dataa;
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assign datab_ipd[datab_width-1:0] = datab;
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initial
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begin
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// 1's padding for 18-bit wide inputs
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i_ones = ~0;
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end
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// get signs of a and b, and get absolute values since Verilog '*' operator
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// is an unsigned multiplication
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assign ia_is_positive = ~signa_ipd | ~dataa_ipd[dataa_width-1];
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assign ib_is_positive = ~signb_ipd | ~datab_ipd[datab_width-1];
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assign iabsa = ia_is_positive == 1 ? dataa_ipd[dataa_width-1:0] : -(dataa_ipd | (i_ones << dataa_width));
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assign iabsb = ib_is_positive == 1 ? datab_ipd[datab_width-1:0] : -(datab_ipd | (i_ones << datab_width));
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// multiply a * b
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assign iabsresult = iabsa * iabsb;
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assign dataout_tmp = (ia_is_positive ^ ib_is_positive) == 1 ? -iabsresult : iabsresult;
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// buf dataout_buf [dataout_width-1:0] (dataout, dataout_tmp);
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assign dataout = dataout_tmp;
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endmodule
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module cycloneiii_mac_mult
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(
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dataa,
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datab,
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signa,
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signb,
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clk,
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aclr,
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ena,
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dataout,
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devclrn,
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devpor
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);
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parameter dataa_width = 18;
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parameter datab_width = 18;
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parameter dataa_clock = "none";
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parameter datab_clock = "none";
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parameter signa_clock = "none";
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parameter signb_clock = "none";
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parameter lpm_hint = "true";
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parameter lpm_type = "cycloneiii_mac_mult";
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// SIMULATION_ONLY_PARAMETERS_BEGIN
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parameter dataout_width = dataa_width + datab_width;
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// SIMULATION_ONLY_PARAMETERS_END
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input [dataa_width-1:0] dataa;
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input [datab_width-1:0] datab;
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input signa;
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input signb;
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input clk;
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input aclr;
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input ena;
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input devclrn;
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input devpor;
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output [dataout_width-1:0] dataout;
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// tri1 devclrn;
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// tri1 devpor;
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wire [dataout_width-1:0] dataout_tmp;
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wire [17:0] idataa_reg; // optional register for dataa input
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wire [17:0] idatab_reg; // optional register for datab input
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wire [17:0] dataa_pad; // padded dataa input
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wire [17:0] datab_pad; // padded datab input
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wire isigna_reg; // optional register for signa input
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wire isignb_reg; // optional register for signb input
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wire [17:0] idataa_int; // dataa as seen by the multiplier input
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wire [17:0] idatab_int; // datab as seen by the multiplier input
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wire isigna_int; // signa as seen by the multiplier input
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wire isignb_int; // signb as seen by the multiplier input
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wire ia_is_positive;
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wire ib_is_positive;
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wire [17:0] iabsa; // absolute value (i.e. positive) form of dataa input
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wire [17:0] iabsb; // absolute value (i.e. positive) form of datab input
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wire [35:0] iabsresult; // absolute value (i.e. positive) form of product (a * b)
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wire dataa_use_reg; // equivalent to dataa_clock parameter
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wire datab_use_reg; // equivalent to datab_clock parameter
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wire signa_use_reg; // equivalent to signa_clock parameter
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wire signb_use_reg; // equivalent to signb_clock parameter
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reg [17:0] i_ones; // padding with 1's for input negation
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wire reg_aclr;
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assign reg_aclr = (!devpor) || (!devclrn) || (aclr);
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// optional registering parameters
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assign dataa_use_reg = (dataa_clock != "none") ? 1'b1 : 1'b0;
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assign datab_use_reg = (datab_clock != "none") ? 1'b1 : 1'b0;
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assign signa_use_reg = (signa_clock != "none") ? 1'b1 : 1'b0;
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assign signb_use_reg = (signb_clock != "none") ? 1'b1 : 1'b0;
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assign dataa_pad = ((18-dataa_width) == 0) ? dataa : {{(18-dataa_width){1'b0}},dataa};
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assign datab_pad = ((18-datab_width) == 0) ? datab : {{(18-datab_width){1'b0}},datab};
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initial
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begin
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// 1's padding for 18-bit wide inputs
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i_ones = ~0;
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end
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// Optional input registers for dataa,b and signa,b
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cycloneiii_mac_data_reg dataa_reg (
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.clk(clk),
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.data(dataa_pad),
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.ena(ena),
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.aclr(reg_aclr),
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.dataout(idataa_reg)
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);
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defparam dataa_reg.data_width = dataa_width;
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cycloneiii_mac_data_reg datab_reg (
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.clk(clk),
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.data(datab_pad),
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.ena(ena),
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.aclr(reg_aclr),
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.dataout(idatab_reg)
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);
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defparam datab_reg.data_width = datab_width;
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cycloneiii_mac_sign_reg signa_reg (
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.clk(clk),
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.d(signa),
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.ena(ena),
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.aclr(reg_aclr),
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.q(isigna_reg)
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);
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cycloneiii_mac_sign_reg signb_reg (
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.clk(clk),
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.d(signb),
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.ena(ena),
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.aclr(reg_aclr),
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.q(isignb_reg)
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);
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// mux input sources from direct inputs or optional registers
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assign idataa_int = dataa_use_reg == 1'b1 ? idataa_reg : dataa;
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assign idatab_int = datab_use_reg == 1'b1 ? idatab_reg : datab;
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assign isigna_int = signa_use_reg == 1'b1 ? isigna_reg : signa;
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assign isignb_int = signb_use_reg == 1'b1 ? isignb_reg : signb;
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cycloneiii_mac_mult_internal mac_multiply (
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.dataa(idataa_int[dataa_width-1:0]),
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.datab(idatab_int[datab_width-1:0]),
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.signa(isigna_int),
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.signb(isignb_int),
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.dataout(dataout)
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);
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defparam mac_multiply.dataa_width = dataa_width;
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defparam mac_multiply.datab_width = datab_width;
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defparam mac_multiply.dataout_width = dataout_width;
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endmodule
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module cycloneiii_mac_out
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(
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dataa,
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clk,
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aclr,
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ena,
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dataout,
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devclrn,
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devpor
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);
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parameter dataa_width = 1;
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parameter output_clock = "none";
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parameter lpm_hint = "true";
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parameter lpm_type = "cycloneiii_mac_out";
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// SIMULATION_ONLY_PARAMETERS_BEGIN
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parameter dataout_width = dataa_width;
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// SIMULATION_ONLY_PARAMETERS_END
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input [dataa_width-1:0] dataa;
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input clk;
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input aclr;
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input ena;
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input devclrn;
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input devpor;
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output [dataout_width-1:0] dataout;
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// tri1 devclrn;
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// tri1 devpor;
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wire [dataa_width-1:0] dataa_ipd; // internal dataa
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wire clk_ipd; // internal clk
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wire aclr_ipd; // internal aclr
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wire ena_ipd; // internal ena
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// internal variable
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wire [dataout_width-1:0] dataout_tmp;
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reg [dataa_width-1:0] idataout_reg; // optional register for dataout output
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wire use_reg; // equivalent to dataout_clock parameter
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wire enable;
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wire no_aclr;
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// Input buffers
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buf (clk_ipd, clk);
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buf (aclr_ipd, aclr);
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buf (ena_ipd, ena);
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// buf dataa_buf [dataa_width-1:0] (dataa_ipd, dataa);
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assign dataa_ipd = dataa;
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// optional registering parameter
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assign use_reg = (output_clock != "none") ? 1 : 0;
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assign enable = (!aclr) && (ena) && use_reg;
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assign no_aclr = (!aclr) && use_reg;
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initial
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begin
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// initial values for optional register
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idataout_reg = 0;
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end
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// Optional input registers for dataa,b and signa,b
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always @* // (posedge clk_ipd or posedge aclr_ipd or negedge devclrn or negedge devpor)
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begin
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if (devclrn == 0 || devpor == 0 || aclr_ipd == 1)
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begin
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idataout_reg <= 0;
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end
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else if (ena_ipd == 1)
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begin
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idataout_reg <= dataa_ipd;
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end
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end
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// mux input sources from direct inputs or optional registers
|
||||
assign dataout_tmp = use_reg == 1 ? idataout_reg : dataa_ipd;
|
||||
|
||||
// accelerate outputs
|
||||
// buf dataout_buf [dataout_width-1:0] (dataout, dataout_tmp);
|
||||
assign dataout = dataout_tmp;
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -81,7 +81,7 @@ done
|
|||
echo "read_ilang ${job}_top_techmap.il"
|
||||
echo "sat -timeout 60 -verify-no-timeout -show a,b,y_rtl,y_syn -prove y_rtl y_syn ${job}_top_nomap"
|
||||
echo "sat -timeout 60 -verify-no-timeout -show a,b,y_rtl,y_syn -prove y_rtl y_syn ${job}_top_techmap"
|
||||
if [[ $job != expression_* ]]; then
|
||||
if [[ $job != expression_* ]] && ! $use_quartus && ! $use_vivado; then
|
||||
echo "eval -brute_force_equiv_checker ${job}_rtl_nomap ${job}_syn_nomap"
|
||||
echo "eval -brute_force_equiv_checker ${job}_rtl_techmap ${job}_syn_techmap"
|
||||
fi
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue