mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-17 09:56:40 +00:00
Code Activity

Merge 52c7ebe734 into 8bb24badf2

Browse source
This commit is contained in:
Martin Povišer 2025-03-10 11:06:41 +13:00 • committed by GitHub
commit cd1ac11a32
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
2 changed files with 6 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

12
passes/techmap/simplemap.cc
View file

@ -415,7 +415,6 @@ void simplemap_get_mappers(dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)>
mappers[ID($or)] = simplemap_bitop; mappers[ID($or)] = simplemap_bitop;
mappers[ID($xor)] = simplemap_bitop; mappers[ID($xor)] = simplemap_bitop;
mappers[ID($xnor)] = simplemap_bitop; mappers[ID($xnor)] = simplemap_bitop;
mappers[ID($bweqx)] = simplemap_bitop;
mappers[ID($reduce_and)] = simplemap_reduce; mappers[ID($reduce_and)] = simplemap_reduce;
mappers[ID($reduce_or)] = simplemap_reduce; mappers[ID($reduce_or)] = simplemap_reduce;
mappers[ID($reduce_xor)] = simplemap_reduce; mappers[ID($reduce_xor)] = simplemap_reduce;
@ -425,9 +424,7 @@ void simplemap_get_mappers(dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)>
mappers[ID($logic_and)] = simplemap_logbin; mappers[ID($logic_and)] = simplemap_logbin;
mappers[ID($logic_or)] = simplemap_logbin; mappers[ID($logic_or)] = simplemap_logbin;
mappers[ID($eq)] = simplemap_eqne; mappers[ID($eq)] = simplemap_eqne;
mappers[ID($eqx)] = simplemap_eqne;
mappers[ID($ne)] = simplemap_eqne; mappers[ID($ne)] = simplemap_eqne;
mappers[ID($nex)] = simplemap_eqne;
mappers[ID($mux)] = simplemap_mux; mappers[ID($mux)] = simplemap_mux;
mappers[ID($bwmux)] = simplemap_bwmux; mappers[ID($bwmux)] = simplemap_bwmux;
mappers[ID($tribuf)] = simplemap_tribuf; mappers[ID($tribuf)] = simplemap_tribuf;
@ -481,11 +478,10 @@ struct SimplemapPass : public Pass {
log("This pass maps a small selection of simple coarse-grain cells to yosys gate\n"); log("This pass maps a small selection of simple coarse-grain cells to yosys gate\n");
log("primitives. The following internal cell types are mapped by this pass:\n"); log("primitives. The following internal cell types are mapped by this pass:\n");
log("\n"); log("\n");
log(" $not, $pos, $and, $or, $xor, $xnor\n"); dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
log(" $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n"); simplemap_get_mappers(mappers);
log(" $logic_not, $logic_and, $logic_or, $mux, $tribuf\n"); for (auto pair : mappers)
log(" $sr, $ff, $dff, $dffe, $dffsr, $dffsre, $adff, $adffe, $aldff, $aldffe, $sdff,\n"); log(" - %s\n", log_id(pair.first));
log(" $sdffe, $sdffce, $dlatch, $adlatch, $dlatchsr\n");
log("\n"); log("\n");
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) override void execute(std::vector<std::string> args, RTLIL::Design *design) override

4
techlibs/common/techmap.v
View file

@ -54,12 +54,12 @@ module _90_simplemap_logic_ops;
endmodule endmodule
(* techmap_simplemap *) (* techmap_simplemap *)
(* techmap_celltype = "$eq $eqx $ne $nex" *) (* techmap_celltype = "$eq $ne" *)
module _90_simplemap_compare_ops; module _90_simplemap_compare_ops;
endmodule endmodule
(* techmap_simplemap *) (* techmap_simplemap *)
(* techmap_celltype = "$pos $slice $concat $mux $tribuf $bmux $bwmux $bweqx" *) (* techmap_celltype = "$pos $slice $concat $mux $tribuf $bmux $bwmux" *)
module _90_simplemap_various; module _90_simplemap_various;
endmodule endmodule