mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-22 08:35:32 +00:00
Code Activity

Makefile

Browse source
This commit is contained in:
Alain Dargelas 2024-11-25 19:37:26 -08:00
parent e9b7db0a4a
commit cd15e211b7
1 changed files with 1 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

4
Makefile
View file

@ -516,9 +516,6 @@ ifneq ($(wildcard $(VERIFIC_DIR)/hier_tree),)
VERIFIC_COMPONENTS += hier_tree
endif
endif
ifeq ($(VERIFIC_LINEFILE_INCLUDES_LOOPS),1)
CXXFLAGS += -DVERIFIC_LINEFILE_INCLUDES_LOOPS
endif
ifeq ($(ENABLE_VERIFIC_SYSTEMVERILOG),1)
VERIFIC_COMPONENTS += verilog
CXXFLAGS += -DVERIFIC_SYSTEMVERILOG_SUPPORT
@ -752,6 +749,7 @@ OBJS += passes/cmds/tee.o
OBJS += passes/cmds/activity.o
OBJS += passes/cmds/splitnetlist.o
OBJS += passes/cmds/reconstructbusses.o
OBJS += passes/cmds/longloop_select.o
OBJS += passes/sat/sim.o
OBJS += passes/techmap/bufnorm.o