mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-24 21:27:00 +00:00
Code Activity

Use choices for addAB, now called postAdd

Browse source
This commit is contained in:
Eddie Hung 2019-09-03 16:10:16 -07:00
parent 2d80866daf
commit cd002ad3fb
2 changed files with 29 additions and 46 deletions
Download patch file Download diff file Expand all files Collapse all files

12
passes/pmgen/xilinx_dsp.cc
View file

@ -39,7 +39,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
log("ffB: %s\n", log_id(st.ffB, "--"));
log("dsp: %s\n", log_id(st.dsp, "--"));
log("ffM: %s\n", log_id(st.ffM, "--"));
log("addAB: %s\n", log_id(st.addAB, "--"));
log("postAdd: %s\n", log_id(st.postAdd, "--"));
log("muxAB: %s\n", log_id(st.muxAB, "--"));
log("ffP: %s\n", log_id(st.ffP, "--"));
//log("muxP: %s\n", log_id(st.muxP, "--"));
@ -53,10 +53,10 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
SigSpec C = st.sigC;
SigSpec P = st.sigP;
if (st.addAB) {
log_assert(st.addAB->getParam("\\A_SIGNED").as_bool());
log_assert(st.addAB->getParam("\\B_SIGNED").as_bool());
log(" adder %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
if (st.postAdd) {
log_assert(st.postAdd->getParam("\\A_SIGNED").as_bool());
log_assert(st.postAdd->getParam("\\B_SIGNED").as_bool());
log(" adder %s (%s)\n", log_id(st.postAdd), log_id(st.postAdd->type));
SigSpec &opmode = cell->connections_.at("\\OPMODE");
if (st.ffP && st.muxAB) {
@ -72,7 +72,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
opmode[6] = State::S0;
opmode[5] = State::S1;
pm.autoremove(st.addAB);
pm.autoremove(st.postAdd);
}
if (st.clock != SigBit())