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https://github.com/YosysHQ/yosys
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[wip] sim model testing
Signed-off-by: David Shah <dave@ds0.me>
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David Shah
parent
fe95807f16
commit
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3 changed files with 361 additions and 41 deletions
1
techlibs/xilinx/tests/.gitignore
vendored
1
techlibs/xilinx/tests/.gitignore
vendored
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@ -4,3 +4,4 @@ bram1_[0-9]*/
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bram2.log
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bram2_syn.v
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bram2_tb
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dsp_work*/
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310
techlibs/xilinx/tests/test_dsp_model.v
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310
techlibs/xilinx/tests/test_dsp_model.v
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@ -0,0 +1,310 @@
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`timescale 1ns / 1ps
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module testbench;
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parameter integer ACASCREG = 1;
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parameter integer ADREG = 1;
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parameter integer ALUMODEREG = 1;
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parameter integer AREG = 1;
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parameter AUTORESET_PATDET = "NO_RESET";
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parameter A_INPUT = "DIRECT";
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parameter integer BCASCREG = 1;
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parameter integer BREG = 1;
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parameter B_INPUT = "DIRECT";
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parameter integer CARRYINREG = 1;
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parameter integer CARRYINSELREG = 1;
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parameter integer CREG = 1;
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parameter integer DREG = 1;
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parameter integer INMODEREG = 1;
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parameter integer MREG = 1;
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parameter integer OPMODEREG = 1;
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parameter integer PREG = 1;
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parameter SEL_MASK = "MASK";
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parameter SEL_PATTERN = "PATTERN";
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parameter USE_DPORT = "FALSE";
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parameter USE_MULT = "MULTIPLY";
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parameter USE_PATTERN_DETECT = "NO_PATDET";
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parameter USE_SIMD = "ONE48";
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parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
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parameter [47:0] PATTERN = 48'h000000000000;
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parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
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parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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parameter [4:0] IS_INMODE_INVERTED = 5'b0;
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parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
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reg CLK;
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reg CEA1, CEA2, CEAD, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL;
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reg CED, CEINMODE, CEM, CEP;
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reg RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTD, RSTINMODE, RSTM, RSTP;
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reg [29:0] A, ACIN;
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reg [17:0] B, BCIN;
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reg [47:0] C;
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reg [24:0] D;
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reg [47:0] PCIN;
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reg [3:0] ALUMODE;
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reg [2:0] CARRYINSEL;
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reg [4:0] INMODE;
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reg [6:0] OPMODE;
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reg CARRYCASCIN, CARRYIN, MULTSIGNIN;
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output [29:0] ACOUT, REF_ACOUT;
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output [17:0] BCOUT, REF_BCOUT;
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output CARRYCASCOUT, REF_CARRYCASCOUT;
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output [3:0] CARRYOUT, REF_CARRYOUT;
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output MULTSIGNOUT, REF_MULTSIGNOUT;
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output OVERFLOW, REF_OVERFLOW;
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output [47:0] P, REF_P;
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output PATTERNBDETECT, REF_PATTERNBDETECT;
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output PATTERNDETECT, REF_PATTERNDETECT;
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output [47:0] PCOUT, REF_PCOUT;
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output UNDERFLOW, REF_UNDERFLOW;
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integer errcount = 0;
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task clkcycle;
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begin
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#5;
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CLK = ~CLK;
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#10;
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CLK = ~CLK;
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#2;
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if (REF_P !== P) begin
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$display("ERROR at %1t: REF_P=%b UUT_P=%b DIFF=%b", $time, REF_P, P, REF_P ^ P);
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errcount = errcount + 1;
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end
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if (REF_CARRYOUT !== CARRYOUT) begin
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$display("ERROR at %1t: REF_CARRYOUT=%b UUT_CARRYOUT=%b", $time, REF_CARRYOUT, CARRYOUT);
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errcount = errcount + 1;
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end
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#3;
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end
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endtask
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reg config_valid = 0;
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task drc;
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config_valid = 1;
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if (AREG != 2 && INMODE[0]) config_valid = 0;
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if (BREG != 2 && INMODE[4]) config_valid = 0;
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if ((OPMODE[3:2] == 2'b01) ^ (OPMODE[1:0] == 2'b01) == 1'b1) config_valid = 0;
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if ((OPMODE[6:4] == 3'b010) && PREG != 1) config_valid = 0;
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if ((OPMODE[6:4] == 3'b010) && (PREG != 1 || OPMODE[3:0] != 4'b1000)) config_valid = 0;
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endtask
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initial begin
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$dumpfile("test_dsp_model.vcd");
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$dumpvars(0, testbench);
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#2;
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CLK = 1'b0;
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{CEA1, CEA2, CEAD, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL} = 9'b111111111;
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{CED, CEINMODE, CEM, CEP} = 4'b1111;
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{A, B, C, D} = 0;
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{ACIN, BCIN, PCIN} = 0;
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{ALUMODE, CARRYINSEL, INMODE} = 0;
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{OPMODE, CARRYCASCIN, CARRYIN, MULTSIGNIN} = 0;
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{RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTD, RSTINMODE, RSTM, RSTP} = ~0;
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#5;
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CLK = 1'b1;
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#10;
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CLK = 1'b0
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#5;
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CLK = 1'b1;
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#10;
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CLK = 1'b0;
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{RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTD, RSTINMODE, RSTM, RSTP} = 0;
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repeat (300) begin
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clkcycle;
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do begin
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A = $urandom;
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ACIN = $urandom;
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B = $urandom;
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BCIN = $urandom;
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C = {$urandom, $urandom};
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D = $urandom;
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PCIN = {$urandom, $urandom};
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{RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTD, RSTINMODE, RSTM, RSTP} = $urandom & $urandom & $urandom;
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{ALUMODE, CARRYINSEL, INMODE} = $urandom & $urandom & $urandom;
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OPMODE = $urandom;
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{CARRYCASCIN, CARRYIN, MULTSIGNIN} = $urandom;
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drc;
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end while (!config_valid);
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end
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if (errcount == 0) begin
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$display("All tests passed.");
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$finish;
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end else begin
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$display("Caught %1d errors.", errcount);
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$stop;
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end
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end
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DSP48E1 #(
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.ACASCREG (ACASCREG),
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.ADREG (ADREG),
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.ALUMODEREG (ALUMODEREG),
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.AREG (AREG),
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.AUTORESET_PATDET (AUTORESET_PATDET),
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.A_INPUT (A_INPUT),
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.BCASCREG (BCASCREG),
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.BREG (BREG),
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.B_INPUT (B_INPUT),
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.CARRYINREG (CARRYINREG),
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.CARRYINSELREG (CARRYINSELREG),
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.CREG (CREG),
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.DREG (DREG),
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.INMODEREG (INMODEREG),
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.MREG (MREG),
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.OPMODEREG (OPMODEREG),
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.PREG (PREG),
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.SEL_MASK (SEL_MASK),
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.SEL_PATTERN (SEL_PATTERN),
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.USE_DPORT (USE_DPORT),
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.USE_MULT (USE_MULT),
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.USE_PATTERN_DETECT (USE_PATTERN_DETECT),
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.USE_SIMD (USE_SIMD),
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.MASK (MASK),
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.PATTERN (PATTERN),
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.IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED),
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.IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED),
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.IS_CLK_INVERTED (IS_CLK_INVERTED),
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.IS_INMODE_INVERTED (IS_INMODE_INVERTED),
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.IS_OPMODE_INVERTED (IS_OPMODE_INVERTED)
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) ref (
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.ACOUT (REF_ACOUT),
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.BCOUT (REF_BCOUT),
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.CARRYCASCOUT (REF_CARRYCASCOUT),
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.CARRYOUT (REF_CARRYOUT),
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.MULTSIGNOUT (REF_MULTSIGNOUT),
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.OVERFLOW (REF_OVERFLOW),
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.P (REF_P),
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.PATTERNBDETECT(REF_PATTERNBDETECT),
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.PATTERNDETECT (REF_PATTERNDETECT),
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.PCOUT (REF_PCOUT),
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.UNDERFLOW (REF_UNDERFLOW),
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.A (A),
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.ACIN (ACIN),
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.ALUMODE (ALUMODE),
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.B (B),
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.BCIN (BCIN),
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.C (C),
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.CARRYCASCIN (CARRYCASCIN),
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.CEA1 (CEA1),
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.CEA2 (CEA2),
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.CEAD (CEAD),
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.CEALUMODE (CEALUMODE),
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.CEB1 (CEB1),
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.CEB2 (CEB2),
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.CEC (CEC),
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.CECARRYIN (CECARRYIN),
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.CECTRL (CECTRL),
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.CED (CED),
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.CEINMODE (CEINMODE),
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.CEM (CEM),
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.CEP (CEP),
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.CLK (CLK),
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.D (D),
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.INMODE (INMODE),
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.MULTSIGNIN (MULTSIGNIN),
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.OPMODE (OPMODE),
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.PCIN (PCIN),
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.RSTA (RSTA),
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.RSTALLCARRYIN (RSTALLCARRYIN),
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.RSTALUMODE (RSTALUMODE),
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.RSTB (RSTB),
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.RSTC (RSTC),
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.RSTCTRL (RSTCTRL),
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.RSTD (RSTD),
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.RSTINMODE (RSTINMODE),
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.RSTM (RSTM),
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.RSTP (RSTP)
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);
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DSP48E1_UUT #(
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.ACASCREG (ACASCREG),
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.ADREG (ADREG),
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.ALUMODEREG (ALUMODEREG),
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.AREG (AREG),
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.AUTORESET_PATDET (AUTORESET_PATDET),
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.A_INPUT (A_INPUT),
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.BCASCREG (BCASCREG),
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.BREG (BREG),
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.B_INPUT (B_INPUT),
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.CARRYINREG (CARRYINREG),
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.CARRYINSELREG (CARRYINSELREG),
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.CREG (CREG),
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.DREG (DREG),
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.INMODEREG (INMODEREG),
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.MREG (MREG),
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.OPMODEREG (OPMODEREG),
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.PREG (PREG),
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.SEL_MASK (SEL_MASK),
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.SEL_PATTERN (SEL_PATTERN),
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.USE_DPORT (USE_DPORT),
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.USE_MULT (USE_MULT),
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.USE_PATTERN_DETECT (USE_PATTERN_DETECT),
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.USE_SIMD (USE_SIMD),
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.MASK (MASK),
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.PATTERN (PATTERN),
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.IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED),
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.IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED),
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.IS_CLK_INVERTED (IS_CLK_INVERTED),
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.IS_INMODE_INVERTED (IS_INMODE_INVERTED),
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.IS_OPMODE_INVERTED (IS_OPMODE_INVERTED)
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) uut (
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.ACOUT (ACOUT),
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.BCOUT (BCOUT),
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.CARRYCASCOUT (CARRYCASCOUT),
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.CARRYOUT (CARRYOUT),
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.MULTSIGNOUT (MULTSIGNOUT),
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.OVERFLOW (OVERFLOW),
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.P (P),
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.PATTERNBDETECT(PATTERNBDETECT),
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.PATTERNDETECT (PATTERNDETECT),
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.PCOUT (PCOUT),
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.UNDERFLOW (UNDERFLOW),
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.A (A),
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.ACIN (ACIN),
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.ALUMODE (ALUMODE),
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.B (B),
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.BCIN (BCIN),
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.C (C),
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.CARRYCASCIN (CARRYCASCIN),
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.CEA1 (CEA1),
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.CEA2 (CEA2),
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.CEAD (CEAD),
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.CEALUMODE (CEALUMODE),
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.CEB1 (CEB1),
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.CEB2 (CEB2),
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.CEC (CEC),
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.CECARRYIN (CECARRYIN),
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.CECTRL (CECTRL),
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.CED (CED),
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.CEINMODE (CEINMODE),
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.CEM (CEM),
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.CEP (CEP),
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.CLK (CLK),
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.D (D),
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.INMODE (INMODE),
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.MULTSIGNIN (MULTSIGNIN),
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.OPMODE (OPMODE),
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.PCIN (PCIN),
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.RSTA (RSTA),
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.RSTALLCARRYIN (RSTALLCARRYIN),
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.RSTALUMODE (RSTALUMODE),
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.RSTB (RSTB),
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.RSTC (RSTC),
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.RSTCTRL (RSTCTRL),
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.RSTD (RSTD),
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.RSTINMODE (RSTINMODE),
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.RSTM (RSTM),
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.RSTP (RSTP)
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);
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endmodule
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