Merge from upstream

tests/.gitignore

@@ -1,2 +1,4 @@
 *.log
+*.out
+*.err
 run-test.mk

tests/aiger/.gitignore

@@ -1,3 +1,2 @@
 /*_ref.v
-/*.log
 /neg.out/

tests/arch/anlogic/.gitignore

@@ -1,4 +1,2 @@
-*.log
-/run-test.mk
 +*_synth.v
 +*_testbench

tests/arch/ecp5/.gitignore

@@ -1,2 +0,0 @@
-*.log
-/run-test.mk

tests/arch/efinix/.gitignore

@@ -1,3 +0,0 @@
-/*.log
-/*.out
-/run-test.mk

tests/arch/fabulous/.gitignore

@@ -1,4 +1,2 @@
-*.log
-/run-test.mk
 +*_synth.v
 +*_testbench

tests/arch/gatemate/.gitignore

@@ -1,4 +1,2 @@
-*.log
-/run-test.mk
 +*_synth.v
 +*_testbench

tests/arch/gowin/.gitignore

@@ -1,3 +0,0 @@
-/*.log
-/*.out
-/run-test.mk

tests/arch/ice40/.gitignore

@@ -1,5 +1,3 @@
-*.log
 *.json
-/run-test.mk
 +*_synth.v
 +*_testbench

tests/arch/intel_alm/.gitignore

@@ -1,2 +0,0 @@
-/*.log
-/run-test.mk

tests/arch/machxo2/.gitignore

@@ -1,2 +0,0 @@
-*.log
-/run-test.mk

tests/arch/microchip/.gitignore

@@ -1,4 +1,2 @@
-*.log
-/run-test.mk
 *.vm
 

tests/arch/nanoxplore/.gitignore

@@ -1,2 +0,0 @@
-*.log
-/run-test.mk

tests/arch/nexus/.gitignore

@@ -1,2 +0,0 @@
-/*.log
-/run-test.mk

tests/arch/quicklogic/.gitignore

@@ -1,4 +1,2 @@
-*.log
-run-test.mk
 +*_synth.v
 +*_testbench

tests/arch/xilinx/.gitignore

@@ -1,5 +1,3 @@
-/*.log
-/*.out
 /run-test.mk
 /*_uut.v
 /test_macc

tests/asicworld/.gitignore

@@ -1,2 +0,0 @@
-*.log
-*.out

tests/bind/.gitignore

@@ -1,2 +0,0 @@
-*.log
-run-test.mk

tests/blif/.gitignore

@@ -1 +0,0 @@
-*.log

tests/bugpoint/.gitignore

@@ -0,0 +1,5 @@
+bugpoint-case.*
+*.log
+*.err
+*.temp
+run-test.mk

tests/bugpoint/failures.ys

@@ -0,0 +1,29 @@
+write_file fail.temp << EOF
+logger -expect error "Missing -script or -command option." 1
+bugpoint -suffix fail -yosys ../../yosys
+EOF
+exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp
+
+write_file fail.temp << EOF
+logger -expect error "do not crash on this design" 1
+bugpoint -suffix fail -yosys ../../yosys -command "dump"
+EOF
+exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp
+
+write_file fail.temp << EOF
+logger -expect error "returned value 3 instead of expected 7" 1
+bugpoint -suffix fail -yosys ../../yosys -command raise_error -expect-return 7
+EOF
+exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp
+
+write_file fail.temp << EOF
+logger -expect error "not found in the log file!" 1
+bugpoint -suffix fail -yosys ../../yosys -command raise_error -grep "nope"
+EOF
+exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp
+
+write_file fail.temp << EOF
+logger -expect error "not found in stderr log!" 1
+bugpoint -suffix fail -yosys ../../yosys -command raise_error -err-grep "nope"
+EOF
+exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp

tests/bugpoint/mod_constraints.ys

@@ -0,0 +1,83 @@
+read_rtlil mods.il
+select -assert-count 7 w:*
+select -assert-mod-count 3 =*
+select -assert-count 4 c:*
+design -stash base
+
+# everything is removed by default
+design -load base
+bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3
+select -assert-count 1 w:*
+select -assert-mod-count 1 =*
+select -assert-none c:*
+
+# don't remove wires
+design -load base
+bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 -modules -cells
+select -assert-count 3 w:*
+select -assert-mod-count 1 =*
+select -assert-none c:*
+
+# don't remove cells or their connections
+design -load base
+bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 -wires -modules
+select -assert-count 5 w:*
+select -assert-mod-count 1 =*
+select -assert-count 4 c:*
+
+# don't remove cells but do remove their connections
+design -load base
+bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 -wires -modules -connections
+select -assert-count 1 w:*
+select -assert-mod-count 1 =*
+select -assert-count 4 c:*
+
+# don't remove modules
+design -load base
+bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 -wires -cells
+select -assert-count 1 w:*
+select -assert-mod-count 3 =*
+select -assert-none c:*
+
+# can keep wires
+design -load base
+setattr -set bugpoint_keep 1 w:w_b
+bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3
+select -assert-count 2 w:*
+select -assert-mod-count 1 =*
+select -assert-none c:*
+
+# a wire with keep won't keep the cell/module containing it
+design -load base
+setattr -set bugpoint_keep 1 w:w_o
+bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3
+select -assert-count 1 w:*
+select -assert-mod-count 1 =*
+select -assert-none c:*
+
+# can keep cells (and do it without the associated module)
+design -load base
+setattr -set bugpoint_keep 1 c:c_a
+bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3
+select -assert-count 1 w:*
+select -assert-mod-count 1 =*
+select -assert-count 1 c:*
+
+# can keep modules
+design -load base
+setattr -mod -set bugpoint_keep 1 m_a
+bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3
+select -assert-count 1 w:*
+select -assert-mod-count 2 =*
+select -assert-none c:*
+
+# minimize to just the path connecting w_a and w_c
+# which happens via w_b, w_i, w_o, m_a, c_a and c_b
+write_file script.temp << EOF
+select -assert-none w:w_a %co* w:w_c %ci* %i
+EOF
+design -load base
+bugpoint -suffix mods -yosys ../../yosys -script script.temp -grep "Assertion failed"
+select -assert-count 5 w:*
+select -assert-mod-count 2 =*
+select -assert-count 2 c:*

tests/bugpoint/mods.il

@@ -0,0 +1,38 @@
+module \m_a
+    wire input 1 \w_i
+    wire output 2 \w_o
+    connect \w_o \w_i
+end
+
+module \m_b
+    wire input 1 \w_i
+    wire output 2 \w_o
+end
+
+attribute \top 1
+module \top
+    attribute \raise_error 3
+    wire \w_a
+    wire \w_b
+    wire \w_c
+
+    cell \m_a \c_a
+        connect \w_i \w_a
+        connect \w_o \w_b
+    end
+
+    cell \m_a \c_b
+        connect \w_i \w_b
+        connect \w_o \w_c
+    end
+
+    cell \m_b \c_c
+        connect \w_i \w_c
+        connect \w_o \w_a
+    end
+
+    cell \m_b \c_d
+        connect \w_i 1'0
+        connect \w_o 1'1
+    end
+end

tests/bugpoint/proc_constraints.ys

@@ -0,0 +1,49 @@
+read_rtlil procs.il
+select -assert-count 2 p:*
+design -stash err_q
+
+# processes get removed by default
+design -load err_q
+bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4
+select -assert-none p:*
+
+# individual processes can be kept
+design -load err_q
+setattr -set bugpoint_keep 1 p:proc_a
+bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4
+select -assert-count 1 p:*
+
+# all processes can be kept
+design -load err_q
+bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -wires
+select -assert-count 2 p:*
+
+# d and clock are connected after proc
+design -load err_q
+proc
+select -assert-count 3 w:d %co
+select -assert-count 3 w:clock %co
+
+# no assigns means no d
+design -load err_q
+bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -assigns
+proc
+select -assert-count 1 w:d %co
+
+# no updates means no clock
+design -load err_q
+bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -updates
+proc
+select -assert-count 1 w:clock %co
+
+# can remove ports
+design -load err_q
+select -assert-count 5 x:*
+bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -ports
+select -assert-none x:*
+
+# can keep ports
+design -load err_q
+setattr -set bugpoint_keep 1 i:d o:q
+bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -ports
+select -assert-count 2 x:*

tests/bugpoint/procs.il

@@ -0,0 +1,42 @@
+module \ff_with_en_and_sync_reset
+  wire $0\q[1:1]
+  wire $0\q[0:0]
+  attribute \raise_error 4
+  wire width 2 output 5 \q
+  wire width 2 input 4 \d
+  wire input 3 \enable
+  wire input 2 \reset
+  wire input 1 \clock
+
+  process \proc_a
+    assign $0\q[0:0] \q [0]
+    switch \reset
+      case 1'1
+        assign $0\q[0:0] 1'0
+      case 
+        switch \enable
+          case 1'1
+            assign $0\q[0:0] \d [0]
+          case 
+        end
+    end
+    sync posedge \clock
+      update \q [0] $0\q[0:0]
+  end
+
+  process \proc_b
+    assign $0\q[1:1] \q [1]
+    switch \reset
+      case 1'1
+        assign $0\q[1:1] 1'0
+      case 
+        switch \enable
+          case 1'1
+            assign $0\q[1:1] \d [1]
+          case 
+        end
+    end
+    sync posedge \clock
+      update \q [1] $0\q[1:1]
+  end
+end

tests/bugpoint/raise_error.ys

@@ -0,0 +1,43 @@
+read_verilog -noblackbox << EOF
+(* raise_error=7 *)
+module top();
+endmodule
+
+(* raise_error="help me" *)
+module other();
+endmodule
+
+(* raise_error *)
+module def();
+endmodule
+EOF
+select -assert-mod-count 3 =*
+design -stash read
+
+# raise_error with int exits with status
+design -load read
+bugpoint -suffix error -yosys ../../yosys -command raise_error -expect-return 7
+select -assert-mod-count 1 =*
+select -assert-mod-count 1 top
+
+# raise_error with string prints message and exits with 1
+design -load read
+rename top abc
+bugpoint -suffix error -yosys ../../yosys -command raise_error -grep "help me" -expect-return 1
+select -assert-mod-count 1 =*
+select -assert-mod-count 1 other
+
+# raise_error with no value exits with 1
+design -load read
+rename def zzy
+delete other
+bugpoint -suffix error -yosys ../../yosys -command raise_error -expect-return 1
+select -assert-mod-count 1 =*
+select -assert-mod-count 1 zzy
+
+# raise_error -stderr prints to stderr and exits with 1
+design -load read
+rename top abc
+bugpoint -suffix error -yosys ../../yosys -command "raise_error -stderr" -err-grep "help me" -expect-return 1
+select -assert-mod-count 1 =*
+select -assert-mod-count 1 other

tests/bugpoint/run-test.sh

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+#!/usr/bin/env bash
+set -eu
+source ../gen-tests-makefile.sh
+generate_mk --yosys-scripts

tests/fmt/.gitignore

@@ -1,3 +1,2 @@
-*.log
 iverilog-*
 yosys-*

tests/hana/.gitignore

@@ -1,2 +0,0 @@
-*.log
-*.out

tests/liberty/.gitignore

@@ -1,3 +1,2 @@
-*.log
 /*.filtered
 *.verilogsim

tests/lut/.gitignore

@@ -1 +0,0 @@
-*.log

tests/memlib/.gitignore

@@ -1,5 +1,2 @@
-t_*.log
-t_*.out
 t_*.v
 t_*.ys
-run-test.mk

tests/memories/.gitignore

@@ -1,3 +1 @@
-*.log
-*.out
 *.dmp

tests/peepopt/.gitignore

@@ -1 +0,0 @@
-/*.log

tests/proc/.gitignore

@@ -1 +0,0 @@
-*.log

tests/rpc/.gitignore

@@ -1 +0,0 @@
-*.log

tests/sat/.gitignore

@@ -1,4 +1,2 @@
-*.log
-run-test.mk
 *.vcd
 *.fst

tests/select/.gitignore

@@ -1 +0,0 @@
-/*.log

tests/sim/.gitignore

@@ -1,6 +1,3 @@
-*.log
-/run-test.mk
 +*_synth.v
 +*_testbench
-*.out
 *.fst

tests/simple/.gitignore

@@ -1,3 +0,0 @@
-*.log
-*.out
-*.err

tests/simple_abc9/.gitignore

@@ -1,5 +1,3 @@
 *.v
 *.sv
-*.log
-*.out
 *.bak

tests/svtypes/.gitignore

@@ -1,3 +0,0 @@
-/*.log
-/*.out
-/run-test.mk

tests/techmap/.gitignore

@@ -1,3 +0,0 @@
-*.log
-*.out
-/*.mk

tests/various/.gitignore

@@ -4,7 +4,6 @@
 /*.sel
 /write_gzip.v
 /write_gzip.v.gz
-/run-test.mk
 /plugin.so
 /plugin.so.dSYM
 /temp

tests/verific/.gitignore

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-/*.log
-/*.out
-/run-test.mk

tests/verilog/.gitignore

@@ -1,7 +1,3 @@
-/*.log
-/*.out
-/*.err
-/run-test.mk
 /const_arst.v
 /const_sr.v
 /doubleslash.v