mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-25 00:22:34 +00:00
Code Activity

Merge from upstream

Browse source
This commit is contained in:
Akash Levy 2025-07-30 22:50:14 -07:00
commit cc733fd11b
63 changed files with 1139 additions and 132 deletions
Download patch file Download diff file Expand all files Collapse all files

23
backends/verilog/verilog_backend.cc
View file

@ -1180,9 +1180,9 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ~((");
dump_cell_expr_port(f, cell, "A", false);
f << stringf(cell->type == ID($_AOI3_) ? " & " : " | ");
f << (cell->type == ID($_AOI3_) ? " & " : " | ");
dump_cell_expr_port(f, cell, "B", false);
f << stringf(cell->type == ID($_AOI3_) ? ") |" : ") &");
f << (cell->type == ID($_AOI3_) ? ") |" : ") &");
dump_attributes(f, "", cell->attributes, " ");
f << stringf(" ");
dump_cell_expr_port(f, cell, "C", false);
@ -1195,13 +1195,13 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ~((");
dump_cell_expr_port(f, cell, "A", false);
f << stringf(cell->type == ID($_AOI4_) ? " & " : " | ");
f << (cell->type == ID($_AOI4_) ? " & " : " | ");
dump_cell_expr_port(f, cell, "B", false);
f << stringf(cell->type == ID($_AOI4_) ? ") |" : ") &");
f << (cell->type == ID($_AOI4_) ? ") |" : ") &");
dump_attributes(f, "", cell->attributes, " ");
f << stringf(" (");
dump_cell_expr_port(f, cell, "C", false);
f << stringf(cell->type == ID($_AOI4_) ? " & " : " | ");
f << (cell->type == ID($_AOI4_) ? " & " : " | ");
dump_cell_expr_port(f, cell, "D", false);
f << stringf("));\n");
return true;
@ -1412,10 +1412,10 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
int s_width = cell->getPort(ID::S).size();
std::string func_name = cellname(cell);
f << stringf("%s" "function [%d:0] %s;\n", indent.c_str(), width-1, func_name.c_str());
f << stringf("%s" " input [%d:0] a;\n", indent.c_str(), width-1);
f << stringf("%s" " input [%d:0] b;\n", indent.c_str(), s_width*width-1);
f << stringf("%s" " input [%d:0] s;\n", indent.c_str(), s_width-1);
f << stringf("%s" "function [%d:0] %s;\n", indent, width-1, func_name);
f << stringf("%s" " input [%d:0] a;\n", indent, width-1);
f << stringf("%s" " input [%d:0] b;\n", indent, s_width*width-1);
f << stringf("%s" " input [%d:0] s;\n", indent, s_width-1);
dump_attributes(f, indent + " ", cell->attributes);
if (noparallelcase)
@ -1424,7 +1424,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (!noattr)
f << stringf("%s" " (* parallel_case *)\n", indent.c_str());
f << stringf("%s" " casez (s)", indent.c_str());
f << stringf(noattr ? " // synopsys parallel_case\n" : "\n");
f << (noattr ? " // synopsys parallel_case\n" : "\n");
}
for (int i = 0; i < s_width; i++)
@ -2637,7 +2637,7 @@ struct VerilogBackend : public Backend {
Pass::call(design, "clean_zerowidth");
log_pop();
design->sort();
design->sort_modules();
*f << stringf("/* Generated by %s */\n", yosys_maybe_version());
@ -2650,6 +2650,7 @@ struct VerilogBackend : public Backend {
continue;
}
log("Dumping module `%s'.\n", module->name.c_str());
module->sort();
dump_module(*f, "", module);
}