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tests: fix the rest

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This commit is contained in:
Emil J. Tywoniak 2026-02-07 01:17:35 +01:00
parent cf2431ac2d
commit cc5ebf8ee8
16 changed files with 36 additions and 10 deletions
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2
tests/sat/asserts.ys
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@ -1,3 +1,3 @@
read_verilog -sv asserts.v
hierarchy; proc; opt; async2sync
hierarchy; proc; opt; async2sync; formalff -clk2ff
sat -verify -seq 1 -set-at 1 rst 1 -tempinduct -prove-asserts

2
tests/sat/asserts_seq.ys
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@ -1,5 +1,5 @@
read_verilog -sv asserts_seq.v
hierarchy; proc; opt; async2sync
hierarchy; proc; opt; async2sync; formalff -clk2ff
sat -verify -prove-asserts -tempinduct -seq 1 test_001
sat -falsify -prove-asserts -tempinduct -seq 1 test_002

1
tests/sat/counters-repeat.ys
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@ -4,6 +4,7 @@ proc; opt
expose -shared counter1 counter2
miter -equiv -make_assert -make_outputs counter1 counter2 miter
formalff -clk2ff
cd miter; flatten; opt
sat -verify -prove-asserts -tempinduct -set-at 1 in_rst 1 -seq 1 -show-inputs -show-outputs

1
tests/sat/counters.ys
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@ -4,6 +4,7 @@ proc; opt
expose -shared counter1 counter2
miter -equiv -make_assert -make_outputs counter1 counter2 miter
formalff -clk2ff
cd miter; flatten; opt
sat -verify -prove-asserts -tempinduct -set-at 1 in_rst 1 -seq 1 -show-inputs -show-outputs

2
tests/sat/dff.ys
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@ -18,4 +18,4 @@ endmodule
EOT
# This ensures that 1) coarse cells have SAT models, 2) fine cells have SAT models, 3) they're equivalent
equiv_opt -assert simplemap
equiv_opt -formalff -assert simplemap