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	Added RTLIL NEW_WIRE macro
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					 2 changed files with 13 additions and 0 deletions
				
			
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					@ -382,6 +382,15 @@ RTLIL::Module *RTLIL::Module::clone() const
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	return new_mod;
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						return new_mod;
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}
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					}
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					RTLIL::SigSpec RTLIL::Module::new_wire(int width, RTLIL::IdString name)
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					{
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						RTLIL::Wire *wire = new RTLIL::Wire;
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						wire->width = width;
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						wire->name = name;
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						add(wire);
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						return wire;
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					}
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void RTLIL::Module::add(RTLIL::Wire *wire)
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					void RTLIL::Module::add(RTLIL::Wire *wire)
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{
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					{
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	assert(!wire->name.empty());
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						assert(!wire->name.empty());
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					@ -129,6 +129,9 @@ namespace RTLIL
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#define NEW_ID \
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					#define NEW_ID \
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	RTLIL::new_id(__FILE__, __LINE__, __FUNCTION__)
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						RTLIL::new_id(__FILE__, __LINE__, __FUNCTION__)
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					#define NEW_WIRE(_mod, _width) \
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						(_mod)->new_wire(_width, NEW_ID)
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	template <typename T> struct sort_by_name {
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						template <typename T> struct sort_by_name {
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		bool operator()(T *a, T *b) const {
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							bool operator()(T *a, T *b) const {
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			return a->name < b->name;
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								return a->name < b->name;
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					@ -244,6 +247,7 @@ struct RTLIL::Module {
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	virtual size_t count_id(RTLIL::IdString id);
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						virtual size_t count_id(RTLIL::IdString id);
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	virtual void check();
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						virtual void check();
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	virtual void optimize();
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						virtual void optimize();
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						RTLIL::SigSpec new_wire(int width, RTLIL::IdString name);
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	void add(RTLIL::Wire *wire);
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						void add(RTLIL::Wire *wire);
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	void add(RTLIL::Cell *cell);
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						void add(RTLIL::Cell *cell);
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	void fixup_ports();
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						void fixup_ports();
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