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Renamed RTLIL::{Module,Cell}::connections to connections_

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This commit is contained in:
Clifford Wolf 2014-07-26 11:58:03 +02:00
parent 665759fcee
commit cc4f10883b
62 changed files with 1234 additions and 1213 deletions
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28
passes/memory/memory_collect.cc
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@ -76,12 +76,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
wr_ports++;
del_cells.push_back(cell);
RTLIL::SigSpec clk = cell->connections["\\CLK"];
RTLIL::SigSpec clk = cell->connections_["\\CLK"];
RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]);
RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]);
RTLIL::SigSpec addr = cell->connections["\\ADDR"];
RTLIL::SigSpec data = cell->connections["\\DATA"];
RTLIL::SigSpec en = cell->connections["\\EN"];
RTLIL::SigSpec addr = cell->connections_["\\ADDR"];
RTLIL::SigSpec data = cell->connections_["\\DATA"];
RTLIL::SigSpec en = cell->connections_["\\EN"];
clk.extend(1, false);
clk_enable.extend(1, false);
@ -103,12 +103,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
rd_ports++;
del_cells.push_back(cell);
RTLIL::SigSpec clk = cell->connections["\\CLK"];
RTLIL::SigSpec clk = cell->connections_["\\CLK"];
RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]);
RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]);
RTLIL::SigSpec transparent = RTLIL::SigSpec(cell->parameters["\\TRANSPARENT"]);
RTLIL::SigSpec addr = cell->connections["\\ADDR"];
RTLIL::SigSpec data = cell->connections["\\DATA"];
RTLIL::SigSpec addr = cell->connections_["\\ADDR"];
RTLIL::SigSpec data = cell->connections_["\\DATA"];
clk.extend(1, false);
clk_enable.extend(1, false);
@ -147,10 +147,10 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 0);
mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : RTLIL::Const(0, 0);
mem->connections["\\WR_CLK"] = sig_wr_clk;
mem->connections["\\WR_ADDR"] = sig_wr_addr;
mem->connections["\\WR_DATA"] = sig_wr_data;
mem->connections["\\WR_EN"] = sig_wr_en;
mem->connections_["\\WR_CLK"] = sig_wr_clk;
mem->connections_["\\WR_ADDR"] = sig_wr_addr;
mem->connections_["\\WR_DATA"] = sig_wr_data;
mem->connections_["\\WR_EN"] = sig_wr_en;
assert(sig_rd_clk.size() == rd_ports);
assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const());
@ -163,9 +163,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : RTLIL::Const(0, 0);
mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : RTLIL::Const(0, 0);
mem->connections["\\RD_CLK"] = sig_rd_clk;
mem->connections["\\RD_ADDR"] = sig_rd_addr;
mem->connections["\\RD_DATA"] = sig_rd_data;
mem->connections_["\\RD_CLK"] = sig_rd_clk;
mem->connections_["\\RD_ADDR"] = sig_rd_addr;
mem->connections_["\\RD_DATA"] = sig_rd_data;
for (auto c : del_cells)
module->remove(c);