mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-24 13:18:56 +00:00
Renamed RTLIL::{Module,Cell}::connections to connections_
This commit is contained in:
Clifford Wolf
parent
665759fcee
commit
cc4f10883b
62 changed files with 1234 additions and 1213 deletions
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@ -76,12 +76,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
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wr_ports++;
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del_cells.push_back(cell);
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RTLIL::SigSpec clk = cell->connections["\\CLK"];
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RTLIL::SigSpec clk = cell->connections_["\\CLK"];
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RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]);
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RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]);
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RTLIL::SigSpec addr = cell->connections["\\ADDR"];
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RTLIL::SigSpec data = cell->connections["\\DATA"];
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RTLIL::SigSpec en = cell->connections["\\EN"];
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RTLIL::SigSpec addr = cell->connections_["\\ADDR"];
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RTLIL::SigSpec data = cell->connections_["\\DATA"];
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RTLIL::SigSpec en = cell->connections_["\\EN"];
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clk.extend(1, false);
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clk_enable.extend(1, false);
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@ -103,12 +103,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
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rd_ports++;
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del_cells.push_back(cell);
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RTLIL::SigSpec clk = cell->connections["\\CLK"];
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RTLIL::SigSpec clk = cell->connections_["\\CLK"];
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RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]);
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RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]);
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RTLIL::SigSpec transparent = RTLIL::SigSpec(cell->parameters["\\TRANSPARENT"]);
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RTLIL::SigSpec addr = cell->connections["\\ADDR"];
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RTLIL::SigSpec data = cell->connections["\\DATA"];
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RTLIL::SigSpec addr = cell->connections_["\\ADDR"];
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RTLIL::SigSpec data = cell->connections_["\\DATA"];
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clk.extend(1, false);
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clk_enable.extend(1, false);
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@ -147,10 +147,10 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
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mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 0);
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mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : RTLIL::Const(0, 0);
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mem->connections["\\WR_CLK"] = sig_wr_clk;
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mem->connections["\\WR_ADDR"] = sig_wr_addr;
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mem->connections["\\WR_DATA"] = sig_wr_data;
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mem->connections["\\WR_EN"] = sig_wr_en;
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mem->connections_["\\WR_CLK"] = sig_wr_clk;
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mem->connections_["\\WR_ADDR"] = sig_wr_addr;
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mem->connections_["\\WR_DATA"] = sig_wr_data;
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mem->connections_["\\WR_EN"] = sig_wr_en;
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assert(sig_rd_clk.size() == rd_ports);
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assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const());
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@ -163,9 +163,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
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mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : RTLIL::Const(0, 0);
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mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : RTLIL::Const(0, 0);
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mem->connections["\\RD_CLK"] = sig_rd_clk;
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mem->connections["\\RD_ADDR"] = sig_rd_addr;
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mem->connections["\\RD_DATA"] = sig_rd_data;
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mem->connections_["\\RD_CLK"] = sig_rd_clk;
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mem->connections_["\\RD_ADDR"] = sig_rd_addr;
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mem->connections_["\\RD_DATA"] = sig_rd_data;
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for (auto c : del_cells)
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module->remove(c);
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@ -25,7 +25,7 @@
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static void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig)
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{
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for (auto &conn : module->connections)
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for (auto &conn : module->connections_)
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sig.replace(conn.first, conn.second);
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}
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@ -46,21 +46,21 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
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continue;
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if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
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if (cell->connections["\\CLK"] != clk)
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if (cell->connections_["\\CLK"] != clk)
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continue;
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if (cell->parameters["\\CLK_POLARITY"].as_bool() != clk_polarity)
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continue;
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}
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RTLIL::SigSpec q_norm = cell->connections[after ? "\\D" : "\\Q"];
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RTLIL::SigSpec q_norm = cell->connections_[after ? "\\D" : "\\Q"];
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normalize_sig(module, q_norm);
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RTLIL::SigSpec d = q_norm.extract(bit, &cell->connections[after ? "\\Q" : "\\D"]);
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RTLIL::SigSpec d = q_norm.extract(bit, &cell->connections_[after ? "\\Q" : "\\D"]);
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if (d.size() != 1)
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continue;
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bit = d;
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clk = cell->connections["\\CLK"];
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clk = cell->connections_["\\CLK"];
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clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
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goto replaced_this_bit;
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}
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@ -79,29 +79,29 @@ static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell)
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RTLIL::SigSpec clk = RTLIL::SigSpec(RTLIL::State::Sx);
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bool clk_polarity = 0;
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RTLIL::SigSpec sig_addr = cell->connections["\\ADDR"];
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RTLIL::SigSpec sig_addr = cell->connections_["\\ADDR"];
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if (!find_sig_before_dff(module, sig_addr, clk, clk_polarity)) {
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log("no (compatible) $dff for address input found.\n");
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return;
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}
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RTLIL::SigSpec sig_data = cell->connections["\\DATA"];
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RTLIL::SigSpec sig_data = cell->connections_["\\DATA"];
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if (!find_sig_before_dff(module, sig_data, clk, clk_polarity)) {
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log("no (compatible) $dff for data input found.\n");
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return;
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}
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RTLIL::SigSpec sig_en = cell->connections["\\EN"];
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RTLIL::SigSpec sig_en = cell->connections_["\\EN"];
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if (!find_sig_before_dff(module, sig_en, clk, clk_polarity)) {
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log("no (compatible) $dff for enable input found.\n");
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return;
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}
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if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
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cell->connections["\\CLK"] = clk;
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cell->connections["\\ADDR"] = sig_addr;
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cell->connections["\\DATA"] = sig_data;
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cell->connections["\\EN"] = sig_en;
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cell->connections_["\\CLK"] = clk;
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cell->connections_["\\ADDR"] = sig_addr;
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cell->connections_["\\DATA"] = sig_data;
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cell->connections_["\\EN"] = sig_en;
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cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
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cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
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log("merged $dff to cell.\n");
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@ -128,7 +128,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
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for (auto &cell_it : module->cells) {
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RTLIL::Cell *cell = cell_it.second;
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if (cell->type == "$dff")
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cell->connections["\\Q"].replace(sig, newsig);
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cell->connections_["\\Q"].replace(sig, newsig);
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}
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}
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@ -139,13 +139,13 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
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bool clk_polarity = 0;
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RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx);
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RTLIL::SigSpec sig_data = cell->connections["\\DATA"];
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RTLIL::SigSpec sig_data = cell->connections_["\\DATA"];
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if (find_sig_before_dff(module, sig_data, clk_data, clk_polarity, true) &&
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clk_data != RTLIL::SigSpec(RTLIL::State::Sx))
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{
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disconnect_dff(module, sig_data);
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cell->connections["\\CLK"] = clk_data;
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cell->connections["\\DATA"] = sig_data;
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cell->connections_["\\CLK"] = clk_data;
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cell->connections_["\\DATA"] = sig_data;
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cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
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cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
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cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
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@ -154,12 +154,12 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
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}
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RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx);
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RTLIL::SigSpec sig_addr = cell->connections["\\ADDR"];
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RTLIL::SigSpec sig_addr = cell->connections_["\\ADDR"];
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if (find_sig_before_dff(module, sig_addr, clk_addr, clk_polarity) &&
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clk_addr != RTLIL::SigSpec(RTLIL::State::Sx))
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{
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cell->connections["\\CLK"] = clk_addr;
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cell->connections["\\ADDR"] = sig_addr;
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cell->connections_["\\CLK"] = clk_addr;
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cell->connections_["\\ADDR"] = sig_addr;
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cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
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cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
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cell->parameters["\\TRANSPARENT"] = RTLIL::Const(1);
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@ -62,20 +62,20 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
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}
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// all write ports must share the same clock
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RTLIL::SigSpec clocks = cell->connections["\\WR_CLK"];
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RTLIL::SigSpec clocks = cell->connections_["\\WR_CLK"];
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RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"];
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RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"];
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RTLIL::SigSpec refclock;
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RTLIL::State refclock_pol = RTLIL::State::Sx;
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for (int i = 0; i < clocks.size(); i++) {
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RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(i * mem_width, mem_width);
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RTLIL::SigSpec wr_en = cell->connections_["\\WR_EN"].extract(i * mem_width, mem_width);
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if (wr_en.is_fully_const() && !wr_en.as_bool()) {
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static_ports.insert(i);
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continue;
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}
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if (clocks_en.bits[i] != RTLIL::State::S1) {
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RTLIL::SigSpec wr_addr = cell->connections["\\WR_ADDR"].extract(i*mem_abits, mem_abits);
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RTLIL::SigSpec wr_data = cell->connections["\\WR_DATA"].extract(i*mem_width, mem_width);
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RTLIL::SigSpec wr_addr = cell->connections_["\\WR_ADDR"].extract(i*mem_abits, mem_abits);
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RTLIL::SigSpec wr_data = cell->connections_["\\WR_DATA"].extract(i*mem_width, mem_width);
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if (wr_addr.is_fully_const()) {
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// FIXME: Actually we should check for wr_en.is_fully_const() also and
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// create a $adff cell with this ports wr_en input as reset pin when wr_en
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@ -120,10 +120,10 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
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c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
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if (clocks_pol.bits.size() > 0) {
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c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]);
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c->connections["\\CLK"] = clocks.extract(0, 1);
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c->connections_["\\CLK"] = clocks.extract(0, 1);
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} else {
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c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1);
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c->connections["\\CLK"] = RTLIL::SigSpec(RTLIL::State::S0);
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c->connections_["\\CLK"] = RTLIL::SigSpec(RTLIL::State::S0);
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}
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RTLIL::Wire *w_in = new RTLIL::Wire;
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@ -131,7 +131,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
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w_in->width = mem_width;
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module->wires[w_in->name] = w_in;
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data_reg_in.push_back(RTLIL::SigSpec(w_in));
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c->connections["\\D"] = data_reg_in.back();
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c->connections_["\\D"] = data_reg_in.back();
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RTLIL::Wire *w_out = new RTLIL::Wire;
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w_out->name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i);
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@ -141,7 +141,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
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w_out->start_offset = mem_offset;
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module->wires[w_out->name] = w_out;
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data_reg_out.push_back(RTLIL::SigSpec(w_out));
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c->connections["\\Q"] = data_reg_out.back();
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c->connections_["\\Q"] = data_reg_out.back();
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}
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}
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@ -151,10 +151,10 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
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for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++)
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{
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RTLIL::SigSpec rd_addr = cell->connections["\\RD_ADDR"].extract(i*mem_abits, mem_abits);
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RTLIL::SigSpec rd_addr = cell->connections_["\\RD_ADDR"].extract(i*mem_abits, mem_abits);
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std::vector<RTLIL::SigSpec> rd_signals;
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rd_signals.push_back(cell->connections["\\RD_DATA"].extract(i*mem_width, mem_width));
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rd_signals.push_back(cell->connections_["\\RD_DATA"].extract(i*mem_width, mem_width));
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if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1)
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{
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@ -163,8 +163,8 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
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RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff");
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c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits);
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c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
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c->connections["\\CLK"] = cell->connections["\\RD_CLK"].extract(i, 1);
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c->connections["\\D"] = rd_addr;
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c->connections_["\\CLK"] = cell->connections_["\\RD_CLK"].extract(i, 1);
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c->connections_["\\D"] = rd_addr;
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count_dff++;
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RTLIL::Wire *w = new RTLIL::Wire;
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@ -172,7 +172,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
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w->width = mem_abits;
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module->wires[w->name] = w;
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c->connections["\\Q"] = RTLIL::SigSpec(w);
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c->connections_["\\Q"] = RTLIL::SigSpec(w);
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rd_addr = RTLIL::SigSpec(w);
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}
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else
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@ -180,8 +180,8 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
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RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff");
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c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
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c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
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c->connections["\\CLK"] = cell->connections["\\RD_CLK"].extract(i, 1);
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c->connections["\\Q"] = rd_signals.back();
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c->connections_["\\CLK"] = cell->connections_["\\RD_CLK"].extract(i, 1);
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c->connections_["\\Q"] = rd_signals.back();
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count_dff++;
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RTLIL::Wire *w = new RTLIL::Wire;
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@ -191,7 +191,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
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rd_signals.clear();
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rd_signals.push_back(RTLIL::SigSpec(w));
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c->connections["\\D"] = rd_signals.back();
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c->connections_["\\D"] = rd_signals.back();
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}
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}
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@ -203,31 +203,31 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux");
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c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
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c->connections["\\Y"] = rd_signals[k];
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c->connections["\\S"] = rd_addr.extract(mem_abits-j-1, 1);
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c->connections_["\\Y"] = rd_signals[k];
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c->connections_["\\S"] = rd_addr.extract(mem_abits-j-1, 1);
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count_mux++;
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RTLIL::Wire *w = new RTLIL::Wire;
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w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$a");
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w->width = mem_width;
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module->wires[w->name] = w;
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c->connections["\\A"] = RTLIL::SigSpec(w);
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c->connections_["\\A"] = RTLIL::SigSpec(w);
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w = new RTLIL::Wire;
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w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$b");
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w->width = mem_width;
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module->wires[w->name] = w;
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c->connections["\\B"] = RTLIL::SigSpec(w);
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c->connections_["\\B"] = RTLIL::SigSpec(w);
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next_rd_signals.push_back(c->connections["\\A"]);
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next_rd_signals.push_back(c->connections["\\B"]);
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next_rd_signals.push_back(c->connections_["\\A"]);
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next_rd_signals.push_back(c->connections_["\\B"]);
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}
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next_rd_signals.swap(rd_signals);
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}
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for (int j = 0; j < mem_size; j++)
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module->connections.push_back(RTLIL::SigSig(rd_signals[j], data_reg_out[j]));
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module->connections_.push_back(RTLIL::SigSig(rd_signals[j], data_reg_out[j]));
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}
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log(" read interface: %d $dff and %d $mux cells.\n", count_dff, count_mux);
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@ -241,9 +241,9 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
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for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++)
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{
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RTLIL::SigSpec wr_addr = cell->connections["\\WR_ADDR"].extract(j*mem_abits, mem_abits);
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RTLIL::SigSpec wr_data = cell->connections["\\WR_DATA"].extract(j*mem_width, mem_width);
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RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(j*mem_width, mem_width);
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RTLIL::SigSpec wr_addr = cell->connections_["\\WR_ADDR"].extract(j*mem_abits, mem_abits);
|
||||
RTLIL::SigSpec wr_data = cell->connections_["\\WR_DATA"].extract(j*mem_width, mem_width);
|
||||
RTLIL::SigSpec wr_en = cell->connections_["\\WR_EN"].extract(j*mem_width, mem_width);
|
||||
|
||||
RTLIL::Cell *c = module->addCell(genid(cell->name, "$wreq", i, "", j), "$eq");
|
||||
c->parameters["\\A_SIGNED"] = RTLIL::Const(0);
|
||||
|
|
@ -251,14 +251,14 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
|
|||
c->parameters["\\A_WIDTH"] = cell->parameters["\\ABITS"];
|
||||
c->parameters["\\B_WIDTH"] = cell->parameters["\\ABITS"];
|
||||
c->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
|
||||
c->connections["\\A"] = RTLIL::SigSpec(i, mem_abits);
|
||||
c->connections["\\B"] = wr_addr;
|
||||
c->connections_["\\A"] = RTLIL::SigSpec(i, mem_abits);
|
||||
c->connections_["\\B"] = wr_addr;
|
||||
count_wrmux++;
|
||||
|
||||
RTLIL::Wire *w_seladdr = new RTLIL::Wire;
|
||||
w_seladdr->name = genid(cell->name, "$wreq", i, "", j, "$y");
|
||||
module->wires[w_seladdr->name] = w_seladdr;
|
||||
c->connections["\\Y"] = w_seladdr;
|
||||
c->connections_["\\Y"] = w_seladdr;
|
||||
|
||||
int wr_offset = 0;
|
||||
while (wr_offset < wr_en.size())
|
||||
|
|
@ -283,33 +283,33 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
|
|||
c->parameters["\\A_WIDTH"] = RTLIL::Const(1);
|
||||
c->parameters["\\B_WIDTH"] = RTLIL::Const(1);
|
||||
c->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
|
||||
c->connections["\\A"] = w;
|
||||
c->connections["\\B"] = wr_bit;
|
||||
c->connections_["\\A"] = w;
|
||||
c->connections_["\\B"] = wr_bit;
|
||||
|
||||
w = new RTLIL::Wire;
|
||||
w->name = genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y");
|
||||
module->wires[w->name] = w;
|
||||
c->connections["\\Y"] = RTLIL::SigSpec(w);
|
||||
c->connections_["\\Y"] = RTLIL::SigSpec(w);
|
||||
}
|
||||
|
||||
c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux");
|
||||
c->parameters["\\WIDTH"] = wr_width;
|
||||
c->connections["\\A"] = sig.extract(wr_offset, wr_width);
|
||||
c->connections["\\B"] = wr_data.extract(wr_offset, wr_width);
|
||||
c->connections["\\S"] = RTLIL::SigSpec(w);
|
||||
c->connections_["\\A"] = sig.extract(wr_offset, wr_width);
|
||||
c->connections_["\\B"] = wr_data.extract(wr_offset, wr_width);
|
||||
c->connections_["\\S"] = RTLIL::SigSpec(w);
|
||||
|
||||
w = new RTLIL::Wire;
|
||||
w->name = genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y");
|
||||
w->width = wr_width;
|
||||
module->wires[w->name] = w;
|
||||
c->connections["\\Y"] = w;
|
||||
c->connections_["\\Y"] = w;
|
||||
|
||||
sig.replace(wr_offset, w);
|
||||
wr_offset += wr_width;
|
||||
}
|
||||
}
|
||||
|
||||
module->connections.push_back(RTLIL::SigSig(data_reg_in[i], sig));
|
||||
module->connections_.push_back(RTLIL::SigSig(data_reg_in[i], sig));
|
||||
}
|
||||
|
||||
log(" write interface: %d blocks of $eq, $and and $mux cells.\n", count_wrmux);
|
||||
|
|
|
|||
|
|
@ -64,16 +64,16 @@ struct MemoryShareWorker
|
|||
RTLIL::Cell *cell = sig_to_mux.at(sig).first;
|
||||
int bit_idx = sig_to_mux.at(sig).second;
|
||||
|
||||
std::vector<RTLIL::SigBit> sig_a = sigmap(cell->connections.at("\\A"));
|
||||
std::vector<RTLIL::SigBit> sig_b = sigmap(cell->connections.at("\\B"));
|
||||
std::vector<RTLIL::SigBit> sig_s = sigmap(cell->connections.at("\\S"));
|
||||
std::vector<RTLIL::SigBit> sig_y = sigmap(cell->connections.at("\\Y"));
|
||||
std::vector<RTLIL::SigBit> sig_a = sigmap(cell->connections_.at("\\A"));
|
||||
std::vector<RTLIL::SigBit> sig_b = sigmap(cell->connections_.at("\\B"));
|
||||
std::vector<RTLIL::SigBit> sig_s = sigmap(cell->connections_.at("\\S"));
|
||||
std::vector<RTLIL::SigBit> sig_y = sigmap(cell->connections_.at("\\Y"));
|
||||
log_assert(sig_y.at(bit_idx) == sig);
|
||||
|
||||
for (int i = 0; i < int(sig_s.size()); i++)
|
||||
if (state.count(sig_s[i]) && state.at(sig_s[i]) == true) {
|
||||
if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), state, conditions))
|
||||
cell->connections.at("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
|
||||
cell->connections_.at("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
@ -87,7 +87,7 @@ struct MemoryShareWorker
|
|||
new_state[sig_s[i]] = true;
|
||||
|
||||
if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), new_state, conditions))
|
||||
cell->connections.at("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
|
||||
cell->connections_.at("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
|
||||
}
|
||||
|
||||
std::map<RTLIL::SigBit, bool> new_state = state;
|
||||
|
|
@ -95,7 +95,7 @@ struct MemoryShareWorker
|
|||
new_state[sig_s[i]] = false;
|
||||
|
||||
if (find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, conditions))
|
||||
cell->connections.at("\\A").replace(bit_idx, RTLIL::State::Sx);
|
||||
cell->connections_.at("\\A").replace(bit_idx, RTLIL::State::Sx);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
|
@ -141,10 +141,10 @@ struct MemoryShareWorker
|
|||
|
||||
if (cell->type == "$mux" || cell->type == "$pmux")
|
||||
{
|
||||
std::vector<RTLIL::SigBit> sig_a = sigmap(cell->connections.at("\\A"));
|
||||
std::vector<RTLIL::SigBit> sig_b = sigmap(cell->connections.at("\\B"));
|
||||
std::vector<RTLIL::SigBit> sig_s = sigmap(cell->connections.at("\\S"));
|
||||
std::vector<RTLIL::SigBit> sig_y = sigmap(cell->connections.at("\\Y"));
|
||||
std::vector<RTLIL::SigBit> sig_a = sigmap(cell->connections_.at("\\A"));
|
||||
std::vector<RTLIL::SigBit> sig_b = sigmap(cell->connections_.at("\\B"));
|
||||
std::vector<RTLIL::SigBit> sig_s = sigmap(cell->connections_.at("\\S"));
|
||||
std::vector<RTLIL::SigBit> sig_y = sigmap(cell->connections_.at("\\Y"));
|
||||
|
||||
non_feedback_nets.insert(sig_s.begin(), sig_s.end());
|
||||
|
||||
|
|
@ -161,7 +161,7 @@ struct MemoryShareWorker
|
|||
cell->parameters.at("\\MEMID").decode_string() == memid)
|
||||
ignore_data_port = true;
|
||||
|
||||
for (auto conn : cell_it.second->connections)
|
||||
for (auto conn : cell_it.second->connections_)
|
||||
{
|
||||
if (ignore_data_port && conn.first == "\\DATA")
|
||||
continue;
|
||||
|
|
@ -191,8 +191,8 @@ struct MemoryShareWorker
|
|||
if (cell->parameters.at("\\CLK_ENABLE").as_bool())
|
||||
continue;
|
||||
|
||||
RTLIL::SigSpec sig_addr = sigmap(cell->connections.at("\\ADDR"));
|
||||
std::vector<RTLIL::SigBit> sig_data = sigmap(cell->connections.at("\\DATA"));
|
||||
RTLIL::SigSpec sig_addr = sigmap(cell->connections_.at("\\ADDR"));
|
||||
std::vector<RTLIL::SigBit> sig_data = sigmap(cell->connections_.at("\\DATA"));
|
||||
|
||||
for (int i = 0; i < int(sig_data.size()); i++)
|
||||
if (non_feedback_nets.count(sig_data[i]))
|
||||
|
|
@ -212,14 +212,14 @@ struct MemoryShareWorker
|
|||
|
||||
for (auto cell : wr_ports)
|
||||
{
|
||||
RTLIL::SigSpec sig_addr = sigmap_xmux(cell->connections.at("\\ADDR"));
|
||||
RTLIL::SigSpec sig_addr = sigmap_xmux(cell->connections_.at("\\ADDR"));
|
||||
if (!async_rd_bits.count(sig_addr))
|
||||
continue;
|
||||
|
||||
log(" Analyzing write port %s.\n", log_id(cell));
|
||||
|
||||
std::vector<RTLIL::SigBit> cell_data = cell->connections.at("\\DATA");
|
||||
std::vector<RTLIL::SigBit> cell_en = cell->connections.at("\\EN");
|
||||
std::vector<RTLIL::SigBit> cell_data = cell->connections_.at("\\DATA");
|
||||
std::vector<RTLIL::SigBit> cell_en = cell->connections_.at("\\EN");
|
||||
|
||||
int created_conditions = 0;
|
||||
for (int i = 0; i < int(cell_data.size()); i++)
|
||||
|
|
@ -239,7 +239,7 @@ struct MemoryShareWorker
|
|||
|
||||
if (created_conditions) {
|
||||
log(" Added enable logic for %d different cases.\n", created_conditions);
|
||||
cell->connections.at("\\EN") = cell_en;
|
||||
cell->connections_.at("\\EN") = cell_en;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -357,15 +357,15 @@ struct MemoryShareWorker
|
|||
for (int i = 0; i < int(wr_ports.size()); i++)
|
||||
{
|
||||
RTLIL::Cell *cell = wr_ports.at(i);
|
||||
RTLIL::SigSpec addr = sigmap_xmux(cell->connections.at("\\ADDR"));
|
||||
RTLIL::SigSpec addr = sigmap_xmux(cell->connections_.at("\\ADDR"));
|
||||
|
||||
if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable ||
|
||||
(cache_clk_enable && (sigmap(cell->connections.at("\\CLK")) != cache_clk ||
|
||||
(cache_clk_enable && (sigmap(cell->connections_.at("\\CLK")) != cache_clk ||
|
||||
cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity)))
|
||||
{
|
||||
cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool();
|
||||
cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool();
|
||||
cache_clk = sigmap(cell->connections.at("\\CLK"));
|
||||
cache_clk = sigmap(cell->connections_.at("\\CLK"));
|
||||
last_port_by_addr.clear();
|
||||
|
||||
if (cache_clk_enable)
|
||||
|
|
@ -377,7 +377,7 @@ struct MemoryShareWorker
|
|||
log(" Port %d (%s) has addr %s.\n", i, log_id(cell), log_signal(addr));
|
||||
|
||||
log(" Active bits: ");
|
||||
std::vector<RTLIL::SigBit> en_bits = sigmap(cell->connections.at("\\EN"));
|
||||
std::vector<RTLIL::SigBit> en_bits = sigmap(cell->connections_.at("\\EN"));
|
||||
active_bits_on_port.push_back(std::vector<bool>(en_bits.size()));
|
||||
for (int k = int(en_bits.size())-1; k >= 0; k--) {
|
||||
active_bits_on_port[i][k] = en_bits[k].wire != NULL || en_bits[k].data != RTLIL::State::S0;
|
||||
|
|
@ -399,13 +399,13 @@ struct MemoryShareWorker
|
|||
|
||||
// Force this ports addr input to addr directly (skip don't care muxes)
|
||||
|
||||
cell->connections.at("\\ADDR") = addr;
|
||||
cell->connections_.at("\\ADDR") = addr;
|
||||
|
||||
// If any of the ports between `last_i' and `i' write to the same address, this
|
||||
// will have priority over whatever `last_i` wrote. So we need to revisit those
|
||||
// ports and mask the EN bits accordingly.
|
||||
|
||||
RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->connections.at("\\EN"));
|
||||
RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->connections_.at("\\EN"));
|
||||
|
||||
for (int j = last_i+1; j < i; j++)
|
||||
{
|
||||
|
|
@ -420,20 +420,20 @@ struct MemoryShareWorker
|
|||
found_overlapping_bits_i_j:
|
||||
log(" Creating collosion-detect logic for port %d.\n", j);
|
||||
RTLIL::SigSpec is_same_addr = module->addWire(NEW_ID);
|
||||
module->addEq(NEW_ID, addr, wr_ports[j]->connections.at("\\ADDR"), is_same_addr);
|
||||
merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->connections.at("\\EN")));
|
||||
module->addEq(NEW_ID, addr, wr_ports[j]->connections_.at("\\ADDR"), is_same_addr);
|
||||
merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->connections_.at("\\EN")));
|
||||
}
|
||||
}
|
||||
|
||||
// Then we need to merge the (masked) EN and the DATA signals.
|
||||
|
||||
RTLIL::SigSpec merged_data = wr_ports[last_i]->connections.at("\\DATA");
|
||||
RTLIL::SigSpec merged_data = wr_ports[last_i]->connections_.at("\\DATA");
|
||||
if (found_overlapping_bits) {
|
||||
log(" Creating logic for merging DATA and EN ports.\n");
|
||||
merge_en_data(merged_en, merged_data, sigmap(cell->connections.at("\\EN")), sigmap(cell->connections.at("\\DATA")));
|
||||
merge_en_data(merged_en, merged_data, sigmap(cell->connections_.at("\\EN")), sigmap(cell->connections_.at("\\DATA")));
|
||||
} else {
|
||||
RTLIL::SigSpec cell_en = sigmap(cell->connections.at("\\EN"));
|
||||
RTLIL::SigSpec cell_data = sigmap(cell->connections.at("\\DATA"));
|
||||
RTLIL::SigSpec cell_en = sigmap(cell->connections_.at("\\EN"));
|
||||
RTLIL::SigSpec cell_data = sigmap(cell->connections_.at("\\DATA"));
|
||||
for (int k = 0; k < int(en_bits.size()); k++)
|
||||
if (!active_bits_on_port[last_i][k]) {
|
||||
merged_en.replace(k, cell_en.extract(k, 1));
|
||||
|
|
@ -443,14 +443,14 @@ struct MemoryShareWorker
|
|||
|
||||
// Connect the new EN and DATA signals and remove the old write port.
|
||||
|
||||
cell->connections.at("\\EN") = merged_en;
|
||||
cell->connections.at("\\DATA") = merged_data;
|
||||
cell->connections_.at("\\EN") = merged_en;
|
||||
cell->connections_.at("\\DATA") = merged_data;
|
||||
|
||||
module->remove(wr_ports[last_i]);
|
||||
wr_ports[last_i] = NULL;
|
||||
|
||||
log(" Active bits: ");
|
||||
std::vector<RTLIL::SigBit> en_bits = sigmap(cell->connections.at("\\EN"));
|
||||
std::vector<RTLIL::SigBit> en_bits = sigmap(cell->connections_.at("\\EN"));
|
||||
active_bits_on_port.push_back(std::vector<bool>(en_bits.size()));
|
||||
for (int k = int(en_bits.size())-1; k >= 0; k--)
|
||||
log("%c", active_bits_on_port[i][k] ? '1' : '0');
|
||||
|
|
@ -489,7 +489,7 @@ struct MemoryShareWorker
|
|||
std::set<int> considered_port_pairs;
|
||||
|
||||
for (int i = 0; i < int(wr_ports.size()); i++) {
|
||||
std::vector<RTLIL::SigBit> bits = modwalker.sigmap(wr_ports[i]->connections.at("\\EN"));
|
||||
std::vector<RTLIL::SigBit> bits = modwalker.sigmap(wr_ports[i]->connections_.at("\\EN"));
|
||||
for (auto bit : bits)
|
||||
if (bit == RTLIL::State::S1)
|
||||
goto port_is_always_active;
|
||||
|
|
@ -509,12 +509,12 @@ struct MemoryShareWorker
|
|||
RTLIL::Cell *cell = wr_ports.at(i);
|
||||
|
||||
if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable ||
|
||||
(cache_clk_enable && (sigmap(cell->connections.at("\\CLK")) != cache_clk ||
|
||||
(cache_clk_enable && (sigmap(cell->connections_.at("\\CLK")) != cache_clk ||
|
||||
cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity)))
|
||||
{
|
||||
cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool();
|
||||
cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool();
|
||||
cache_clk = sigmap(cell->connections.at("\\CLK"));
|
||||
cache_clk = sigmap(cell->connections_.at("\\CLK"));
|
||||
}
|
||||
else if (i > 0 && considered_ports.count(i-1) && considered_ports.count(i))
|
||||
considered_port_pairs.insert(i);
|
||||
|
|
@ -542,7 +542,7 @@ struct MemoryShareWorker
|
|||
for (int i = 0; i < int(wr_ports.size()); i++)
|
||||
if (considered_port_pairs.count(i) || considered_port_pairs.count(i+1))
|
||||
{
|
||||
RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->connections.at("\\EN"));
|
||||
RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->connections_.at("\\EN"));
|
||||
port_to_sat_variable[i] = ez.expression(ez.OpOr, satgen.importSigSpec(sig));
|
||||
|
||||
std::vector<RTLIL::SigBit> bits = sig;
|
||||
|
|
@ -585,18 +585,18 @@ struct MemoryShareWorker
|
|||
log(" Merging port %d into port %d.\n", i-1, i);
|
||||
port_to_sat_variable.at(i) = ez.OR(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i));
|
||||
|
||||
RTLIL::SigSpec last_addr = wr_ports[i-1]->connections.at("\\ADDR");
|
||||
RTLIL::SigSpec last_data = wr_ports[i-1]->connections.at("\\DATA");
|
||||
std::vector<RTLIL::SigBit> last_en = modwalker.sigmap(wr_ports[i-1]->connections.at("\\EN"));
|
||||
RTLIL::SigSpec last_addr = wr_ports[i-1]->connections_.at("\\ADDR");
|
||||
RTLIL::SigSpec last_data = wr_ports[i-1]->connections_.at("\\DATA");
|
||||
std::vector<RTLIL::SigBit> last_en = modwalker.sigmap(wr_ports[i-1]->connections_.at("\\EN"));
|
||||
|
||||
RTLIL::SigSpec this_addr = wr_ports[i]->connections.at("\\ADDR");
|
||||
RTLIL::SigSpec this_data = wr_ports[i]->connections.at("\\DATA");
|
||||
std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(wr_ports[i]->connections.at("\\EN"));
|
||||
RTLIL::SigSpec this_addr = wr_ports[i]->connections_.at("\\ADDR");
|
||||
RTLIL::SigSpec this_data = wr_ports[i]->connections_.at("\\DATA");
|
||||
std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(wr_ports[i]->connections_.at("\\EN"));
|
||||
|
||||
RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en);
|
||||
|
||||
wr_ports[i]->connections.at("\\ADDR") = module->Mux(NEW_ID, last_addr, this_addr, this_en_active);
|
||||
wr_ports[i]->connections.at("\\DATA") = module->Mux(NEW_ID, last_data, this_data, this_en_active);
|
||||
wr_ports[i]->connections_.at("\\ADDR") = module->Mux(NEW_ID, last_addr, this_addr, this_en_active);
|
||||
wr_ports[i]->connections_.at("\\DATA") = module->Mux(NEW_ID, last_data, this_data, this_en_active);
|
||||
|
||||
std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;
|
||||
RTLIL::SigSpec grouped_last_en, grouped_this_en, en;
|
||||
|
|
@ -614,7 +614,7 @@ struct MemoryShareWorker
|
|||
}
|
||||
|
||||
module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en);
|
||||
wr_ports[i]->connections.at("\\EN") = en;
|
||||
wr_ports[i]->connections_.at("\\EN") = en;
|
||||
|
||||
module->remove(wr_ports[i-1]);
|
||||
wr_ports[i-1] = NULL;
|
||||
|
|
@ -653,18 +653,18 @@ struct MemoryShareWorker
|
|||
|
||||
if (cell->type == "$mux")
|
||||
{
|
||||
RTLIL::SigSpec sig_a = sigmap_xmux(cell->connections.at("\\A"));
|
||||
RTLIL::SigSpec sig_b = sigmap_xmux(cell->connections.at("\\B"));
|
||||
RTLIL::SigSpec sig_a = sigmap_xmux(cell->connections_.at("\\A"));
|
||||
RTLIL::SigSpec sig_b = sigmap_xmux(cell->connections_.at("\\B"));
|
||||
|
||||
if (sig_a.is_fully_undef())
|
||||
sigmap_xmux.add(cell->connections.at("\\Y"), sig_b);
|
||||
sigmap_xmux.add(cell->connections_.at("\\Y"), sig_b);
|
||||
else if (sig_b.is_fully_undef())
|
||||
sigmap_xmux.add(cell->connections.at("\\Y"), sig_a);
|
||||
sigmap_xmux.add(cell->connections_.at("\\Y"), sig_a);
|
||||
}
|
||||
|
||||
if (cell->type == "$mux" || cell->type == "$pmux")
|
||||
{
|
||||
std::vector<RTLIL::SigBit> sig_y = sigmap(cell->connections.at("\\Y"));
|
||||
std::vector<RTLIL::SigBit> sig_y = sigmap(cell->connections_.at("\\Y"));
|
||||
for (int i = 0; i < int(sig_y.size()); i++)
|
||||
sig_to_mux[sig_y[i]] = std::pair<RTLIL::Cell*, int>(cell, i);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -54,9 +54,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
|
|||
cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const();
|
||||
cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_POLARITY")).extract(i, 1).as_const();
|
||||
cell->parameters["\\TRANSPARENT"] = RTLIL::SigSpec(memory->parameters.at("\\RD_TRANSPARENT")).extract(i, 1).as_const();
|
||||
cell->connections["\\CLK"] = memory->connections.at("\\RD_CLK").extract(i, 1);
|
||||
cell->connections["\\ADDR"] = memory->connections.at("\\RD_ADDR").extract(i*abits, abits);
|
||||
cell->connections["\\DATA"] = memory->connections.at("\\RD_DATA").extract(i*mem->width, mem->width);
|
||||
cell->connections_["\\CLK"] = memory->connections_.at("\\RD_CLK").extract(i, 1);
|
||||
cell->connections_["\\ADDR"] = memory->connections_.at("\\RD_ADDR").extract(i*abits, abits);
|
||||
cell->connections_["\\DATA"] = memory->connections_.at("\\RD_DATA").extract(i*mem->width, mem->width);
|
||||
}
|
||||
|
||||
for (int i = 0; i < num_wr_ports; i++)
|
||||
|
|
@ -68,10 +68,10 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
|
|||
cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const();
|
||||
cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_POLARITY")).extract(i, 1).as_const();
|
||||
cell->parameters["\\PRIORITY"] = i;
|
||||
cell->connections["\\CLK"] = memory->connections.at("\\WR_CLK").extract(i, 1);
|
||||
cell->connections["\\EN"] = memory->connections.at("\\WR_EN").extract(i*mem->width, mem->width);
|
||||
cell->connections["\\ADDR"] = memory->connections.at("\\WR_ADDR").extract(i*abits, abits);
|
||||
cell->connections["\\DATA"] = memory->connections.at("\\WR_DATA").extract(i*mem->width, mem->width);
|
||||
cell->connections_["\\CLK"] = memory->connections_.at("\\WR_CLK").extract(i, 1);
|
||||
cell->connections_["\\EN"] = memory->connections_.at("\\WR_EN").extract(i*mem->width, mem->width);
|
||||
cell->connections_["\\ADDR"] = memory->connections_.at("\\WR_ADDR").extract(i*abits, abits);
|
||||
cell->connections_["\\DATA"] = memory->connections_.at("\\WR_DATA").extract(i*mem->width, mem->width);
|
||||
}
|
||||
|
||||
module->remove(memory);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue