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Renamed RTLIL::{Module,Cell}::connections to connections_

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This commit is contained in:
Clifford Wolf 2014-07-26 11:58:03 +02:00
parent 665759fcee
commit cc4f10883b
62 changed files with 1234 additions and 1213 deletions
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18
passes/fsm/fsm_detect.cc
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@ -52,8 +52,8 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig
for (auto &cellport : cellport_list) {
if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux" && cellport.first->type != "$safe_pmux") || cellport.second != "\\Y")
return false;
RTLIL::SigSpec sig_a = assign_map(cellport.first->connections["\\A"]);
RTLIL::SigSpec sig_b = assign_map(cellport.first->connections["\\B"]);
RTLIL::SigSpec sig_a = assign_map(cellport.first->connections_["\\A"]);
RTLIL::SigSpec sig_b = assign_map(cellport.first->connections_["\\B"]);
if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor))
return false;
for (int i = 0; i < sig_b.size(); i += sig_a.size())
@ -80,14 +80,14 @@ static bool check_state_users(RTLIL::SigSpec sig)
continue;
if (cellport.second != "\\A" && cellport.second != "\\B")
return false;
if (cell->connections.count("\\A") == 0 || cell->connections.count("\\B") == 0 || cell->connections.count("\\Y") == 0)
if (cell->connections_.count("\\A") == 0 || cell->connections_.count("\\B") == 0 || cell->connections_.count("\\Y") == 0)
return false;
for (auto &port_it : cell->connections)
for (auto &port_it : cell->connections_)
if (port_it.first != "\\A" && port_it.first != "\\B" && port_it.first != "\\Y")
return false;
if (assign_map(cell->connections["\\A"]) == sig && cell->connections["\\B"].is_fully_const())
if (assign_map(cell->connections_["\\A"]) == sig && cell->connections_["\\B"].is_fully_const())
continue;
if (assign_map(cell->connections["\\B"]) == sig && cell->connections["\\A"].is_fully_const())
if (assign_map(cell->connections_["\\B"]) == sig && cell->connections_["\\A"].is_fully_const())
continue;
return false;
}
@ -109,8 +109,8 @@ static void detect_fsm(RTLIL::Wire *wire)
continue;
muxtree_cells.clear();
SigPool recursion_monitor;
RTLIL::SigSpec sig_q = assign_map(cellport.first->connections["\\Q"]);
RTLIL::SigSpec sig_d = assign_map(cellport.first->connections["\\D"]);
RTLIL::SigSpec sig_q = assign_map(cellport.first->connections_["\\Q"]);
RTLIL::SigSpec sig_d = assign_map(cellport.first->connections_["\\D"]);
if (sig_q == RTLIL::SigSpec(wire) && check_state_mux_tree(sig_q, sig_d, recursion_monitor) && check_state_users(sig_q)) {
log("Found FSM state register %s in module %s.\n", wire->name.c_str(), module->name.c_str());
wire->attributes["\\fsm_encoding"] = RTLIL::Const("auto");
@ -160,7 +160,7 @@ struct FsmDetectPass : public Pass {
sig2user.clear();
sig_at_port.clear();
for (auto &cell_it : module->cells)
for (auto &conn_it : cell_it.second->connections) {
for (auto &conn_it : cell_it.second->connections_) {
if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) {
RTLIL::SigSpec sig = conn_it.second;
assign_map.apply(sig);