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Renamed RTLIL::{Module,Cell}::connections to connections_

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This commit is contained in:
Clifford Wolf 2014-07-26 11:58:03 +02:00
parent 665759fcee
commit cc4f10883b
62 changed files with 1234 additions and 1213 deletions
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10
passes/cmds/show.cc
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@ -344,7 +344,7 @@ struct ShowWorker
std::vector<RTLIL::IdString> in_ports, out_ports;
for (auto &conn : it.second->connections) {
for (auto &conn : it.second->connections_) {
if (!ct.cell_output(it.second->type, conn.first))
in_ports.push_back(conn.first);
else
@ -368,7 +368,7 @@ struct ShowWorker
label_string += "}}";
std::string code;
for (auto &conn : it.second->connections) {
for (auto &conn : it.second->connections_) {
code += gen_portbox(stringf("c%d:p%d", id2num(it.first), id2num(conn.first)),
conn.second, ct.cell_output(it.second->type, conn.first));
}
@ -421,7 +421,7 @@ struct ShowWorker
fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\"];\n", pidx, findLabel(proc->name), proc_src.c_str());
}
for (auto &conn : module->connections)
for (auto &conn : module->connections_)
{
bool found_lhs_wire = false;
for (auto &c : conn.first.chunks()) {
@ -516,7 +516,7 @@ struct ShowWorker
log("Skipping blackbox module %s.\n", id2cstr(module->name));
continue;
} else
if (module->cells.empty() && module->connections.empty() && module->processes.empty()) {
if (module->cells.empty() && module->connections_.empty() && module->processes.empty()) {
log("Skipping empty module %s.\n", id2cstr(module->name));
continue;
} else
@ -695,7 +695,7 @@ struct ShowPass : public Pass {
for (auto &mod_it : design->modules) {
if (mod_it.second->get_bool_attribute("\\blackbox"))
continue;
if (mod_it.second->cells.empty() && mod_it.second->connections.empty())
if (mod_it.second->cells.empty() && mod_it.second->connections_.empty())
continue;
if (design->selected_module(mod_it.first))
modcount++;