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Renamed RTLIL::{Module,Cell}::connections to connections_

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This commit is contained in:
Clifford Wolf 2014-07-26 11:58:03 +02:00
parent 665759fcee
commit cc4f10883b
62 changed files with 1234 additions and 1213 deletions
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4
passes/cmds/select.cc
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@ -380,7 +380,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
if (lhs.selected_member(mod_it.first, it.first) && limits.count(it.first) == 0)
selected_wires.insert(it.second);
for (auto &conn : mod->connections)
for (auto &conn : mod->connections_)
{
std::vector<RTLIL::SigBit> conn_lhs = conn.first.to_sigbit_vector();
std::vector<RTLIL::SigBit> conn_rhs = conn.second.to_sigbit_vector();
@ -396,7 +396,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
}
for (auto &cell : mod->cells)
for (auto &conn : cell.second->connections)
for (auto &conn : cell.second->connections_)
{
char last_mode = '-';
for (auto &rule : rules) {