mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-24 13:18:56 +00:00
Code Activity

Renamed RTLIL::{Module,Cell}::connections to connections_

Browse source
This commit is contained in:
Clifford Wolf 2014-07-26 11:58:03 +02:00
parent 665759fcee
commit cc4f10883b
62 changed files with 1234 additions and 1213 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/cmds/add.cc
View file

@ -75,10 +75,10 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
continue;
if (mod->get_bool_attribute("\\blackbox"))
continue;
if (it.second->connections.count(name) > 0)
if (it.second->connections_.count(name) > 0)
continue;
it.second->connections[name] = wire;
it.second->connections_[name] = wire;
log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str());
}
}