Renamed RTLIL::{Module,Cell}::connections to connections_

passes/cmds/add.cc

@@ -75,10 +75,10 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
 			continue;
 		if (mod->get_bool_attribute("\\blackbox"))
 			continue;
-		if (it.second->connections.count(name) > 0)
+		if (it.second->connections_.count(name) > 0)
 			continue;
 
-		it.second->connections[name] = wire;
+		it.second->connections_[name] = wire;
 		log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str());
 	}
 }

passes/cmds/connect.cc

@@ -30,11 +30,11 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
 	RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size());
 
 	for (auto &it : module->cells)
-	for (auto &port : it.second->connections)
+	for (auto &port : it.second->connections_)
 		if (ct.cell_output(it.second->type, port.first))
 			sigmap(port.second).replace(sig, dummy_wire, &port.second);
 
-	for (auto &conn : module->connections)
+	for (auto &conn : module->connections_)
 		sigmap(conn.first).replace(sig, dummy_wire, &conn.first);
 }
 
@@ -123,7 +123,7 @@ struct ConnectPass : public Pass {
 
 		SigMap sigmap;
 		if (!flag_nomap)
-			for (auto &it : module->connections) {
+			for (auto &it : module->connections_) {
 				std::vector<RTLIL::SigBit> lhs = it.first.to_sigbit_vector();
 				std::vector<RTLIL::SigBit> rhs = it.first.to_sigbit_vector();
 				for (size_t i = 0; i < lhs.size(); i++)
@@ -148,7 +148,7 @@ struct ConnectPass : public Pass {
 			if (!flag_nounset)
 				unset_drivers(design, module, sigmap, sig_lhs);
 
-			module->connections.push_back(RTLIL::SigSig(sig_lhs, sig_rhs));
+			module->connections_.push_back(RTLIL::SigSig(sig_lhs, sig_rhs));
 		}
 		else
 		if (!unset_expr.empty())
@@ -176,7 +176,7 @@ struct ConnectPass : public Pass {
 			if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr))
 				log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str());
 
-			module->cells.at(RTLIL::escape_id(port_cell))->connections[RTLIL::escape_id(port_port)] = sigmap(sig);
+			module->cells.at(RTLIL::escape_id(port_cell))->connections_[RTLIL::escape_id(port_port)] = sigmap(sig);
 		}
 		else
 			log_cmd_error("Expected -set, -unset, or -port.\n");

passes/cmds/connwrappers.cc

@@ -74,7 +74,7 @@ struct ConnwrappersWorker
 			if (!decl_celltypes.count(cell->type))
 				continue;
 
-			for (auto &conn : cell->connections)
+			for (auto &conn : cell->connections_)
 			{
 				std::pair<std::string, std::string> key(cell->type, conn.first);
 
@@ -109,7 +109,7 @@ struct ConnwrappersWorker
 			if (!design->selected(module, cell))
 				continue;
 
-			for (auto &conn : cell->connections)
+			for (auto &conn : cell->connections_)
 			{
 				std::vector<RTLIL::SigBit> sigbits = sigmap(conn.second).to_sigbit_vector();
 				RTLIL::SigSpec old_sig;

passes/cmds/scatter.cc

@@ -49,7 +49,7 @@ struct ScatterPass : public Pass {
 				continue;
 
 			for (auto &c : mod_it.second->cells)
-			for (auto &p : c.second->connections)
+			for (auto &p : c.second->connections_)
 			{
 				RTLIL::Wire *wire = new RTLIL::Wire;
 				wire->name = NEW_ID;
@@ -58,10 +58,10 @@ struct ScatterPass : public Pass {
 
 				if (ct.cell_output(c.second->type, p.first)) {
 					RTLIL::SigSig sigsig(p.second, wire);
-					mod_it.second->connections.push_back(sigsig);
+					mod_it.second->connections_.push_back(sigsig);
 				} else {
 					RTLIL::SigSig sigsig(wire, p.second);
-					mod_it.second->connections.push_back(sigsig);
+					mod_it.second->connections_.push_back(sigsig);
 				}
 
 				p.second = wire;

passes/cmds/scc.cc

@@ -132,7 +132,7 @@ struct SccWorker
 
 			RTLIL::SigSpec inputSignals, outputSignals;
 
-			for (auto &conn : cell->connections)
+			for (auto &conn : cell->connections_)
 			{
 				bool isInput = true, isOutput = true;
 

passes/cmds/select.cc

@@ -380,7 +380,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
 			if (lhs.selected_member(mod_it.first, it.first) && limits.count(it.first) == 0)
 				selected_wires.insert(it.second);
 
-		for (auto &conn : mod->connections)
+		for (auto &conn : mod->connections_)
 		{
 			std::vector<RTLIL::SigBit> conn_lhs = conn.first.to_sigbit_vector();
 			std::vector<RTLIL::SigBit> conn_rhs = conn.second.to_sigbit_vector();
@@ -396,7 +396,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
 		}
 
 		for (auto &cell : mod->cells)
-		for (auto &conn : cell.second->connections)
+		for (auto &conn : cell.second->connections_)
 		{
 			char last_mode = '-';
 			for (auto &rule : rules) {

passes/cmds/setundef.cc

@@ -135,7 +135,7 @@ struct SetundefPass : public Pass {
 
 				CellTypes ct(design);
 				for (auto &it : module->cells)
-				for (auto &conn : it.second->connections)
+				for (auto &conn : it.second->connections_)
 					if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
 						undriven_signals.del(sigmap(conn.second));
 
@@ -144,7 +144,7 @@ struct SetundefPass : public Pass {
 					RTLIL::SigSpec bits;
 					for (int i = 0; i < c.width; i++)
 						bits.append(worker.next_bit());
-					module->connections.push_back(RTLIL::SigSig(c, bits));
+					module->connections_.push_back(RTLIL::SigSig(c, bits));
 				}
 			}
 

passes/cmds/show.cc

@@ -344,7 +344,7 @@ struct ShowWorker
 
 			std::vector<RTLIL::IdString> in_ports, out_ports;
 
-			for (auto &conn : it.second->connections) {
+			for (auto &conn : it.second->connections_) {
 				if (!ct.cell_output(it.second->type, conn.first))
 					in_ports.push_back(conn.first);
 				else
@@ -368,7 +368,7 @@ struct ShowWorker
 			label_string += "}}";
 
 			std::string code;
-			for (auto &conn : it.second->connections) {
+			for (auto &conn : it.second->connections_) {
 				code += gen_portbox(stringf("c%d:p%d", id2num(it.first), id2num(conn.first)),
 						conn.second, ct.cell_output(it.second->type, conn.first));
 			}
@@ -421,7 +421,7 @@ struct ShowWorker
 			fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\"];\n", pidx, findLabel(proc->name), proc_src.c_str());
 		}
 
-		for (auto &conn : module->connections)
+		for (auto &conn : module->connections_)
 		{
 			bool found_lhs_wire = false;
 			for (auto &c : conn.first.chunks()) {
@@ -516,7 +516,7 @@ struct ShowWorker
 					log("Skipping blackbox module %s.\n", id2cstr(module->name));
 					continue;
 				} else
-				if (module->cells.empty() && module->connections.empty() && module->processes.empty()) {
+				if (module->cells.empty() && module->connections_.empty() && module->processes.empty()) {
 					log("Skipping empty module %s.\n", id2cstr(module->name));
 					continue;
 				} else
@@ -695,7 +695,7 @@ struct ShowPass : public Pass {
 			for (auto &mod_it : design->modules) {
 				if (mod_it.second->get_bool_attribute("\\blackbox"))
 					continue;
-				if (mod_it.second->cells.empty() && mod_it.second->connections.empty())
+				if (mod_it.second->cells.empty() && mod_it.second->connections_.empty())
 					continue;
 				if (design->selected_module(mod_it.first))
 					modcount++;

passes/cmds/splice.cc

@@ -74,9 +74,9 @@ struct SpliceWorker
 			cell->parameters["\\OFFSET"] = offset;
 			cell->parameters["\\A_WIDTH"] = sig_a.size();
 			cell->parameters["\\Y_WIDTH"] = sig.size();
-			cell->connections["\\A"] = sig_a;
-			cell->connections["\\Y"] = module->addWire(NEW_ID, sig.size());
-			new_sig = cell->connections["\\Y"];
+			cell->connections_["\\A"] = sig_a;
+			cell->connections_["\\Y"] = module->addWire(NEW_ID, sig.size());
+			new_sig = cell->connections_["\\Y"];
 		}
 
 		sliced_signals_cache[sig] = new_sig;
@@ -130,10 +130,10 @@ struct SpliceWorker
 			RTLIL::Cell *cell = module->addCell(NEW_ID, "$concat");
 			cell->parameters["\\A_WIDTH"] = new_sig.size();
 			cell->parameters["\\B_WIDTH"] = sig2.size();
-			cell->connections["\\A"] = new_sig;
-			cell->connections["\\B"] = sig2;
-			cell->connections["\\Y"] = module->addWire(NEW_ID, new_sig.size() + sig2.size());
-			new_sig = cell->connections["\\Y"];
+			cell->connections_["\\A"] = new_sig;
+			cell->connections_["\\B"] = sig2;
+			cell->connections_["\\Y"] = module->addWire(NEW_ID, new_sig.size() + sig2.size());
+			new_sig = cell->connections_["\\Y"];
 		}
 
 		spliced_signals_cache[sig] = new_sig;
@@ -159,7 +159,7 @@ struct SpliceWorker
 			}
 
 		for (auto &it : module->cells)
-		for (auto &conn : it.second->connections)
+		for (auto &conn : it.second->connections_)
 			if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) {
 				RTLIL::SigSpec sig = sigmap(conn.second);
 				driven_chunks.insert(sig);
@@ -182,7 +182,7 @@ struct SpliceWorker
 		for (auto &it : module->cells) {
 			if (!sel_by_wire && !design->selected(module, it.second))
 				continue;
-			for (auto &conn : it.second->connections)
+			for (auto &conn : it.second->connections_)
 				if (ct.cell_input(it.second->type, conn.first)) {
 					if (ports.size() > 0 && !ports.count(conn.first))
 						continue;
@@ -232,7 +232,7 @@ struct SpliceWorker
 			it.first->port_output = false;
 			module->add(it.first);
 			module->add(new_port);
-			module->connections.push_back(RTLIL::SigSig(new_port, it.second));
+			module->connections_.push_back(RTLIL::SigSig(new_port, it.second));
 		}
 	}
 };

passes/cmds/splitnets.cc

@@ -134,7 +134,7 @@ struct SplitnetsPass : public Pass {
 				std::map<RTLIL::Wire*, std::set<int>> split_wires_at;
 
 				for (auto &c : module->cells)
-				for (auto &p : c.second->connections)
+				for (auto &p : c.second->connections_)
 				{
 					if (!ct.cell_known(c.second->type))
 						continue;