mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-23 14:23:41 +00:00
Code Activity

Renamed RTLIL::{Module,Cell}::connections to connections_

Browse source
This commit is contained in:
Clifford Wolf 2014-07-26 11:58:03 +02:00
parent 665759fcee
commit cc4f10883b
62 changed files with 1234 additions and 1213 deletions
Download patch file Download diff file Expand all files Collapse all files

4
backends/ilang/ilang_backend.cc
View file

@ -163,7 +163,7 @@ void ILANG_BACKEND::dump_cell(FILE *f, std::string indent, const RTLIL::Cell *ce
dump_const(f, it->second);
fprintf(f, "\n");
}
for (auto it = cell->connections.begin(); it != cell->connections.end(); it++) {
for (auto it = cell->connections_.begin(); it != cell->connections_.end(); it++) {
fprintf(f, "%s connect %s ", indent.c_str(), it->first.c_str());
dump_sigspec(f, it->second);
fprintf(f, "\n");
@ -309,7 +309,7 @@ void ILANG_BACKEND::dump_module(FILE *f, std::string indent, const RTLIL::Module
}
bool first_conn_line = true;
for (auto it = module->connections.begin(); it != module->connections.end(); it++) {
for (auto it = module->connections_.begin(); it != module->connections_.end(); it++) {
bool show_conn = !only_selected;
if (only_selected) {
RTLIL::SigSpec sigs = it->first;