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Release version 0.35

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Miodrag Milanovic 2023-11-07 08:45:31 +01:00
parent 93a426cbbf
commit cc31c6ebc4
2 changed files with 11 additions and 3 deletions
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CHANGELOG
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@ -2,8 +2,16 @@
List of major changes and improvements between releases
=======================================================
Yosys 0.34 .. Yosys 0.35-dev
Yosys 0.34 .. Yosys 0.35
--------------------------
* Various
- Improvements on "peepopt" shiftmul matcher.
- Improvements on "ram_style" attributes handling.
* Verific support
- Improved static elaboration for VHDL and mixed HDL designs.
- Expose "hdlname" attribute with original module name.
- Expose "architecture" attribute with VHDL architecture name.
Yosys 0.33 .. Yosys 0.34
--------------------------