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	Progress in new BTOR back-end
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					 1 changed files with 74 additions and 16 deletions
				
			
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			@ -56,6 +56,9 @@ struct BtorWorker
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	// nids for constants
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	dict<Const, int> consts;
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	// ff inputs that need to be evaluated (<nid>, <d>)
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	vector<pair<int, SigSpec>> ff_todo;
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	pool<Cell*> cell_recursion_guard;
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	int get_bv_sid(int width)
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			@ -68,16 +71,26 @@ struct BtorWorker
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		return sorts_bv.at(width);
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	}
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	void add_nid_sig(int nid, const SigSpec &sig)
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	{
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		for (int i = 0; i < GetSize(sig); i++)
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			bit_nid[sig[i]] = make_pair(nid, i);
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		sig_nid[sig] = nid;
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		nid_width[nid] = GetSize(sig);
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	}
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	void export_cell(Cell *cell)
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	{
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		log_assert(cell_recursion_guard.count(cell) == 0);
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		cell_recursion_guard.insert(cell);
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		if (cell->type.in("$add", "$sub"))
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		if (cell->type.in("$add", "$sub", "$xor"))
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		{
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			string btor_op;
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			if (cell->type == "$add") btor_op = "add";
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			if (cell->type == "$sub") btor_op = "sub";
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			if (cell->type == "$xor") btor_op = "xor";
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			log_assert(!btor_op.empty());
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			int width = GetSize(cell->getPort("\\Y"));
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			@ -92,27 +105,62 @@ struct BtorWorker
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			int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);
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			int nid = next_nid++;
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			f << stringf("%d %s %d %d %d\n", nid, btor_op.c_str(), sid, nid_a, nid_b);
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			f << stringf("%d %s %d %d %d ; %s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, log_id(cell));
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			SigSpec sig = sigmap(cell->getPort("\\Y"));
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			if (GetSize(sig) < width) {
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				int sid = get_bv_sid(GetSize(sig));
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				int nid2 = next_nid++;
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				f << stringf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
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				f << stringf("%d slice %d %d %d 0 ; %s\n", nid2, sid, nid, GetSize(sig)-1, log_id(cell));
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				nid = nid2;
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			}
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			for (int i = 0; i < GetSize(sig); i++)
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				bit_nid[sig[i]] = make_pair(nid, i);
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			sig_nid[sig] = nid;
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			nid_width[nid] = GetSize(sig);
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			add_nid_sig(nid, sig);
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			goto okay;
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		}
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		log_error("Unsupported cell type: %s\n", log_id(cell));
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		if (cell->type.in("$mux", "$_MUX_"))
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		{
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			SigSpec sig_a = sigmap(cell->getPort("\\A"));
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			SigSpec sig_b = sigmap(cell->getPort("\\B"));
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			SigSpec sig_s = sigmap(cell->getPort("\\S"));
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			SigSpec sig_y = sigmap(cell->getPort("\\Y"));
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			int nid_a = get_sig_nid(sig_a);
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			int nid_b = get_sig_nid(sig_b);
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			int nid_s = get_sig_nid(sig_s);
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			int sid = get_bv_sid(GetSize(sig_y));
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			int nid = next_nid++;
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			f << stringf("%d ite %d %d %d %d ; %s\n", nid, sid, nid_s, nid_b, nid_a, log_id(cell));
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			add_nid_sig(nid, sig_y);
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			goto okay;
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		}
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		if (cell->type.in("$dff", "$ff", "$_DFF_P_", "$_DFF_N", "$_FF_"))
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		{
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			SigSpec sig_d = sigmap(cell->getPort("\\D"));
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			SigSpec sig_q = sigmap(cell->getPort("\\Q"));
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			string symbol = log_signal(sig_q);
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			if (symbol.find(' ') != string::npos)
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				symbol = log_id(cell);
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			if (symbol[0] == '\\')
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				symbol = symbol.substr(1);
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			int sid = get_bv_sid(GetSize(sig_q));
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			int nid = next_nid++;
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			f << stringf("%d state %d %s ; %s\n", nid, sid, symbol.c_str(), log_id(cell));
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			ff_todo.push_back(make_pair(nid, sig_d));
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			add_nid_sig(nid, sig_q);
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			goto okay;
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		}
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		log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
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	okay:
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		cell_recursion_guard.erase(cell);
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			@ -146,6 +194,7 @@ struct BtorWorker
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							int nid = next_nid++;
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							f << stringf("%d const %d %s\n", nid, sid, c.as_string().c_str());
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							consts[c] = nid;
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							nid_width[nid] = GetSize(c);
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						}
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						int nid = consts.at(c);
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			@ -182,7 +231,7 @@ struct BtorWorker
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				int nid3 = nid2;
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				if (lower != 0 && upper+1 != nid_width.at(nid2)) {
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				if (lower != 0 || upper+1 != nid_width.at(nid2)) {
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					int sid = get_bv_sid(upper-lower+1);
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					nid3 = next_nid++;
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					f << stringf("%d slice %d %d %d %d\n", nid3, sid, nid, upper, lower);
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			@ -241,11 +290,7 @@ struct BtorWorker
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			int nid = next_nid++;
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			f << stringf("%d input %d %s\n", nid, sid, log_id(wire));
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			for (int i = 0; i < GetSize(sig); i++)
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				bit_nid[sig[i]] = make_pair(nid, i);
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			sig_nid[sig] = nid;
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			nid_width[nid] = GetSize(sig);
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			add_nid_sig(nid, sig);
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		}
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		for (auto cell : module->cells())
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			@ -266,6 +311,19 @@ struct BtorWorker
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			int nid = get_sig_nid(wire);
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			f << stringf("%d output %d %s\n", next_nid++, nid, log_id(wire));
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		}
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		while (!ff_todo.empty())
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		{
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			vector<pair<int, SigSpec>> todo;
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			todo.swap(ff_todo);
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			for (auto &it : todo)
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			{
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				int nid = get_sig_nid(it.second);
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				int sid = get_bv_sid(GetSize(it.second));
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				f << stringf("%d next %d %d %d\n", next_nid++, sid, it.first, nid);
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			}
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		}
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	}
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};
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