mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-24 21:27:00 +00:00
Code Activity

Make a few passes auto-call Mem::narrow instead of rejecting wide ports.

Browse source 
This essentially adds wide port support for free in passes that don't
have a usefully better way of handling wide ports than just breaking
them up to narrow ports, avoiding "please run memory_narrow" annoyance.
This commit is contained in:
Marcelina Kościelnicka 2021-05-27 23:43:25 +02:00
parent 055ba748bc
commit cbf6b719fe
5 changed files with 10 additions and 33 deletions
Download patch file Download diff file Expand all files Collapse all files

15
passes/memory/memory_bram.cc
View file

@ -1052,6 +1052,7 @@ grow_read_ports:;
void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
{
log("Processing %s.%s:\n", log_id(mem.module), log_id(mem.memid));
mem.narrow();
bool cell_init = !mem.inits.empty();
@ -1069,20 +1070,6 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
log(" %s=%d", it.first.c_str(), it.second);
log("\n");
for (auto &port : mem.rd_ports) {
if (port.wide_log2) {
log("Wide read ports are not supported, skipping.\n");
return;
}
}
for (auto &port : mem.wr_ports) {
if (port.wide_log2) {
log("Wide write ports are not supported, skipping.\n");
return;
}
}
// This pass cannot deal with write port priority — we need to emulate it,
// if present. Since priority emulation will change the enable signals,
// which in turn may change enable grouping and mapping eligibility in