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Make a few passes auto-call Mem::narrow instead of rejecting wide ports.

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This essentially adds wide port support for free in passes that don't
have a usefully better way of handling wide ports than just breaking
them up to narrow ports, avoiding "please run memory_narrow" annoyance.
This commit is contained in:
Marcelina Kościelnicka 2021-05-27 23:43:25 +02:00
parent 055ba748bc
commit cbf6b719fe
5 changed files with 10 additions and 33 deletions
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6
backends/firrtl/firrtl.cc
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@ -542,6 +542,8 @@ struct FirrtlWorker
vector<string> port_decls, wire_decls, mem_exprs, cell_exprs, wire_exprs;
std::vector<Mem> memories = Mem::get_all_memories(module);
for (auto &mem : memories)
mem.narrow();
for (auto wire : module->wires())
{
@ -993,8 +995,6 @@ struct FirrtlWorker
if (port.clk_enable)
log_error("Clocked read port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid));
if (port.wide_log2 != 0)
log_error("Wide read port %d on memory %s.%s. Use memory_narrow to convert them first.\n", i, log_id(module), log_id(mem.memid));
std::ostringstream rpe;
@ -1016,8 +1016,6 @@ struct FirrtlWorker
if (!port.clk_enable)
log_error("Unclocked write port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid));
if (port.wide_log2 != 0)
log_error("Wide write port %d on memory %s.%s. Use memory_narrow to convert them first.\n", i, log_id(module), log_id(mem.memid));
if (!port.clk_polarity)
log_error("Negedge write port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid));
for (int i = 1; i < GetSize(port.en); i++)