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aiger: add regression test for sliced output segfault

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This commit is contained in:
Emil Jiří Tywoniak 2025-05-09 16:01:47 +02:00
parent 2522bcd492
commit cbf069849e
1 changed files with 10 additions and 0 deletions
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10
tests/aiger/io.ys Normal file
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@ -0,0 +1,10 @@
read_verilog <<EOF
module bad(
input in,
output reg [1:0] out
);
assign out = {in, 1'b0};
endmodule
EOF
proc
write_aiger -vmap /dev/null /dev/null