mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-18 09:12:18 +00:00
Code Activity

presentation progress

Browse source
This commit is contained in:
Clifford Wolf 2014-01-29 12:15:38 +01:00
parent aceab5fc08
commit cbe77bf844
10 changed files with 174 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

23
manual/PRESENTATION_Intro/mycells.v Normal file
View file

@ -0,0 +1,23 @@
module NOT(A, Y);
input A;
output Y = ~A;
endmodule
module NAND(A, B, Y);
input A, B;
output Y = ~(A & B);
endmodule
module NOR(A, B, Y);
input A, B;
output Y = ~(A | B);
endmodule
module DFF(C, D, Q);
input C, D;
output reg Q;
always @(posedge C)
Q <= D;
endmodule