mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-11 05:30:53 +00:00
Code Activity

presentation progress

Browse source
This commit is contained in:
Clifford Wolf 2014-01-29 12:15:38 +01:00
parent aceab5fc08
commit cbe77bf844
10 changed files with 174 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

26
manual/PRESENTATION_Intro/counter.ys Normal file
View file

@ -0,0 +1,26 @@
# read design
read_verilog counter.v
hierarchy -check -top counter
show -format pdf -prefix counter_00
# the high-level stuff
proc; opt; memory; opt; fsm; opt
show -format pdf -prefix counter_01
# mapping to internal cell library
techmap; splitnets -ports; opt
show -format pdf -prefix counter_02
# mapping flip-flops to mycells.lib
dfflibmap -liberty mycells.lib
# mapping logic to mycells.lib
abc -liberty mycells.lib
# cleanup
clean
show -lib mycells.v -format pdf -prefix counter_03