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opt_merge: avoid hashing strings

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This commit is contained in:
Emil J. Tywoniak 2024-10-18 16:25:15 +02:00
parent 8bb24badf2
commit cbb776c626
1 changed files with 90 additions and 83 deletions
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173
passes/opt/opt_merge.cc
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@ -26,6 +26,8 @@
#include <stdlib.h> #include <stdlib.h>
#include <stdio.h> #include <stdio.h>
#include <set> #include <set>
#include <unordered_map>
#include <array>
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
@ -42,6 +44,22 @@ struct OptMergeWorker
CellTypes ct; CellTypes ct;
int total_count; int total_count;
static vector<pair<SigBit, SigSpec>> sorted_pmux_in(const dict<RTLIL::IdString, RTLIL::SigSpec> &conn)
{
SigSpec sig_s = conn.at(ID::S);
SigSpec sig_b = conn.at(ID::B);
int s_width = GetSize(sig_s);
int width = GetSize(sig_b) / s_width;
vector<pair<SigBit, SigSpec>> sb_pairs;
for (int i = 0; i < s_width; i++)
sb_pairs.push_back(pair<SigBit, SigSpec>(sig_s[i], sig_b.extract(i*width, width)));
std::sort(sb_pairs.begin(), sb_pairs.end());
return sb_pairs;
}
static void sort_pmux_conn(dict<RTLIL::IdString, RTLIL::SigSpec> &conn) static void sort_pmux_conn(dict<RTLIL::IdString, RTLIL::SigSpec> &conn)
{ {
SigSpec sig_s = conn.at(ID::S); SigSpec sig_s = conn.at(ID::S);
@ -65,90 +83,74 @@ struct OptMergeWorker
} }
} }
std::string int_to_hash_string(unsigned int v) Hasher hash_cell_inputs(const RTLIL::Cell *cell, Hasher h)
{ {
if (v == 0) // TODO: when implemented, use celltypes to match:
return "0"; // (builtin || stdcell) && (unary || binary) && symmetrical
std::string str = "";
while (v > 0) {
str += 'a' + (v & 15);
v = v >> 4;
}
return str;
}
uint64_t hash_cell_parameters_and_connections(const RTLIL::Cell *cell)
{
vector<string> hash_conn_strings;
std::string hash_string = cell->type.str() + "\n";
const dict<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
dict<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul), if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul),
ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) { ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) {
alt_conn = *conn; std::array<RTLIL::SigSpec, 2> inputs = {
if (assign_map(alt_conn.at(ID::A)) < assign_map(alt_conn.at(ID::B))) { assign_map(cell->getPort(ID::A)),
alt_conn[ID::A] = conn->at(ID::B); assign_map(cell->getPort(ID::B))
alt_conn[ID::B] = conn->at(ID::A); };
std::sort(inputs.begin(), inputs.end());
h = hash_ops<std::array<RTLIL::SigSpec, 2>>::hash_acc(inputs, h);
h = assign_map(cell->getPort(ID::Y)).hash_acc(h);
} else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
SigSpec a = assign_map(cell->getPort(ID::A));
a.sort();
h = a.hash_acc(h);
} else if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
SigSpec a = assign_map(cell->getPort(ID::A));
a.sort_and_unify();
h = a.hash_acc(h);
} else if (cell->type == ID($pmux)) {
dict<RTLIL::IdString, RTLIL::SigSpec> conn = cell->connections();
assign_map.apply(conn.at(ID::A));
assign_map.apply(conn.at(ID::B));
assign_map.apply(conn.at(ID::S));
for (const auto& [s_bit, b_chunk] : sorted_pmux_in(conn)) {
h = s_bit.hash_acc(h);
h = b_chunk.hash_acc(h);
} }
conn = &alt_conn; h = assign_map(cell->getPort(ID::A)).hash_acc(h);
} else } else {
if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) { std::vector<std::pair<IdString, SigSpec>> conns;
alt_conn = *conn; for (const auto& conn : cell->connections()) {
assign_map.apply(alt_conn.at(ID::A)); conns.push_back(conn);
alt_conn.at(ID::A).sort(); }
conn = &alt_conn; std::sort(conns.begin(), conns.end());
} else for (const auto& [port, sig] : conns) {
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) { if (!cell->output(port)) {
alt_conn = *conn; h = port.hash_acc(h);
assign_map.apply(alt_conn.at(ID::A)); h = assign_map(sig).hash_acc(h);
alt_conn.at(ID::A).sort_and_unify();
conn = &alt_conn;
} else
if (cell->type == ID($pmux)) {
alt_conn = *conn;
assign_map.apply(alt_conn.at(ID::A));
assign_map.apply(alt_conn.at(ID::B));
assign_map.apply(alt_conn.at(ID::S));
sort_pmux_conn(alt_conn);
conn = &alt_conn;
}
for (auto &it : *conn) {
RTLIL::SigSpec sig;
if (cell->output(it.first)) {
if (it.first == ID::Q && RTLIL::builtin_ff_cell_types().count(cell->type)) {
// For the 'Q' output of state elements,
// use its (* init *) attribute value
sig = initvals(it.second);
} }
else
continue;
} }
else
sig = assign_map(it.second); if (RTLIL::builtin_ff_cell_types().count(cell->type))
string s = "C " + it.first.str() + "="; h = initvals(cell->getPort(ID::Q)).hash_acc(h);
for (auto &chunk : sig.chunks()) {
if (chunk.wire)
s += "{" + chunk.wire->name.str() + " " +
int_to_hash_string(chunk.offset) + " " +
int_to_hash_string(chunk.width) + "}";
else
s += RTLIL::Const(chunk.data).as_string();
}
hash_conn_strings.push_back(s + "\n");
} }
return h;
}
for (auto &it : cell->parameters) static Hasher hash_cell_parameters(const RTLIL::Cell *cell, Hasher h)
hash_conn_strings.push_back("P " + it.first.str() + "=" + it.second.as_string() + "\n"); {
using Paramvec = std::vector<std::pair<IdString, Const>>;
Paramvec params;
for (const auto& param : cell->parameters) {
params.push_back(param);
}
std::sort(params.begin(), params.end());
return hash_ops<Paramvec>::hash_acc(params, h);
}
std::sort(hash_conn_strings.begin(), hash_conn_strings.end()); Hasher hash_cell_function(const RTLIL::Cell *cell, Hasher h)
{
for (auto it : hash_conn_strings) h.eat(cell->type);
hash_string += it; h = hash_cell_inputs(cell, h);
h = hash_cell_parameters(cell, h);
return std::hash<std::string>{}(hash_string); return h;
} }
bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2) bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2)
@ -255,18 +257,23 @@ struct OptMergeWorker
while (did_something) while (did_something)
{ {
std::vector<RTLIL::Cell*> cells; std::vector<RTLIL::Cell*> cells;
cells.reserve(module->cells_.size()); cells.reserve(module->cells().size());
for (auto &it : module->cells_) { for (auto cell : module->cells()) {
if (!design->selected(module, it.second)) if (!design->selected(module, cell))
continue; continue;
if (mode_keepdc && has_dont_care_initval(it.second)) if (cell->type.in(ID($meminit), ID($meminit_v2), ID($mem), ID($mem_v2))) {
// Ignore those for performance: meminit can have an excessively large port,
// mem can have an excessively large parameter holding the init data
continue; continue;
if (ct.cell_known(it.second->type) || (mode_share_all && it.second->known())) }
cells.push_back(it.second); if (mode_keepdc && has_dont_care_initval(cell))
continue;
if (ct.cell_known(cell->type) || (mode_share_all && cell->known()))
cells.push_back(cell);
} }
did_something = false; did_something = false;
dict<uint64_t, RTLIL::Cell*> sharemap; dict<Hasher::hash_t, RTLIL::Cell*> sharemap;
for (auto cell : cells) for (auto cell : cells)
{ {
if ((!mode_share_all && !ct.cell_known(cell->type)) || !cell->known()) if ((!mode_share_all && !ct.cell_known(cell->type)) || !cell->known())
@ -275,7 +282,7 @@ struct OptMergeWorker
if (cell->type == ID($scopeinfo)) if (cell->type == ID($scopeinfo))
continue; continue;
uint64_t hash = hash_cell_parameters_and_connections(cell); Hasher::hash_t hash = hash_cell_function(cell, Hasher()).yield();
auto r = sharemap.insert(std::make_pair(hash, cell)); auto r = sharemap.insert(std::make_pair(hash, cell));
if (!r.second) { if (!r.second) {
if (compare_cell_parameters_and_connections(cell, r.first->second)) { if (compare_cell_parameters_and_connections(cell, r.first->second)) {