mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 20:38:44 +00:00
Code Activity

Updating initial state and checks

Browse source
This commit is contained in:
Miodrag Milanovic 2022-01-31 09:19:34 +01:00
parent 190e44f0da
commit cbadfa0268
1 changed files with 28 additions and 15 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
passes/sat/sim.cc
View file

@ -1016,6 +1016,18 @@ struct SimWorker : SimShared
log_error("Stop time is before start time\n");
}
auto edges = fst->getAllEdges(fst_clock, startCount, stopCount);
if ((startCount == stopCount) && writeback) {
log("Update initial state with values from %zu\n",startCount);
if (edges.empty())
edges.push_back(startCount);
fst->reconstructAllAtTimes(edges);
top->setInitState(startCount);
pool<Module*> wbmods;
top->writeback(wbmods);
} else {
if (edges.empty())
log_error("No clock edges found in given time range\n");
fst->reconstructAllAtTimes(edges);
bool initial = false;
for(auto &time : edges) {
@ -1034,6 +1046,7 @@ struct SimWorker : SimShared
log_error("Signal difference at %zu\n", time);
}
}
}
};
struct SimPass : public Pass {