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Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now

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This commit is contained in:
dh73 2017-10-01 11:04:17 -05:00
parent c5b204d8d2
commit cbaba62401
31 changed files with 2969 additions and 729 deletions
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33
techlibs/intel/common/brams.txt Executable file
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bram $__M9K_ALTSYNCRAM_SINGLEPORT_FULL
init 1
abits 13 @M1
dbits 1 @M1
abits 12 @M2
dbits 2 @M2
abits 11 @M3
dbits 4 @M3
abits 10 @M4
dbits 8 @M4
abits 10 @M5
dbits 9 @M5
abits 9 @M6
dbits 16 @M6
abits 9 @M7
dbits 18 @M7
abits 8 @M8
dbits 32 @M8
abits 8 @M9
dbits 36 @M9
groups 2
ports 1 1
wrmode 0 1
enable 1 1
transp 0 0
clocks 2 3
clkpol 2 3
endbram
match $__M9K_ALTSYNCRAM_SINGLEPORT_FULL
min efficiency 2
make_transp
endmatch