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Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now

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dh73 2017-10-01 11:04:17 -05:00
parent c5b204d8d2
commit cbaba62401
31 changed files with 2969 additions and 729 deletions
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22
techlibs/intel/Makefile.inc Executable file
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OBJS += techlibs/intel/synth_intel.o
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/m9k_bb.v))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/altpll_bb.v))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams.txt))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map.v))
$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_sim.v))
$(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_sim.v))
$(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_sim.v))
$(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/cells_sim.v))
$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/cells_sim.v))
$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_map.v))
$(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_map.v))
$(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_map.v))
$(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/cells_map.v))
$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/cells_map.v))
#$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/arith_map.v))
#$(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/arith_map.v))
#$(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/arith_map.v))
#$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v))

65
techlibs/intel/a10gx/cells_arith.v Executable file
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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// NOTE: This is still WIP.
(* techmap_celltype = "$alu" *)
module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
//output [Y_WIDTH-1:0] CO;
output CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
wire [Y_WIDTH+1:0] C = {COx, CI};
/* Start implementation */
(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
if(i==Y_WIDTH-1) begin
(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH]));
assign CO = COx[Y_WIDTH];
end
else
fiftyfivenm_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1]));
end: slice
endgenerate
/* End implementation */
assign X = AA ^ BB;
endmodule

53
techlibs/intel/a10gx/cells_map.v Executable file
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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// Input buffer map
module \$__inpad (input I, output O);
twentynm_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
endmodule
// Output buffer map
module \$__outpad (input I, output O);
twentynm_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
endmodule
// LUT Map
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else
if (WIDTH == 2) begin
twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off"))
_TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1), .datae(1'b1), .dataf(1'b1), .datag(1'b1));
end /*else
if(WIDTH == 3) begin
fiftyfivenm_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));
end else
if(WIDTH == 4) begin
fiftyfivenm_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3]));
end*/ else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule //

59
techlibs/intel/a10gx/cells_sim.v Executable file
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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module VCC (output V);
assign V = 1'b1;
endmodule // VCC
module GND (output G);
assign G = 1'b0;
endmodule // GND
/* Altera Arria 10 GX devices Input Buffer Primitive */
module twentynm_io_ibuf (output o, input i, input ibar);
assign ibar = ibar;
assign o = i;
endmodule // twentynm_io_ibuf
/* Altera Arria 10 GX devices Output Buffer Primitive */
module twentynm_io_obuf (output o, input i, input oe);
assign o = i;
assign oe = oe;
endmodule // twentynm_io_obuf
/* Altera Arria 10 GX LUT Primitive */
module twentynm_lcell_comb (output combout, cout, sumout,
input dataa, datab, datac, datad,
input datae, dataf, datag, cin,
input sharein);
parameter lut_mask = 64'hFFFFFFFFFFFFFFFF;
parameter dont_touch = "off";
parameter lpm_type = "twentynm_lcell_comb";
parameter shared_arith = "off";
parameter extended_lut = "off";
// TODO: This is still WIP
initial begin
$display("Simulation model is still under investigation\n");
end
endmodule // twentynm_lcell_comb

366
techlibs/intel/common/altpll_bb.v Normal file
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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
/* No clearbox model */
`ifdef NO_CLEARBOX
(* blackbox *)
module altpll
( inclk,
fbin,
pllena,
clkswitch,
areset,
pfdena,
clkena,
extclkena,
scanclk,
scanaclr,
scanclkena,
scanread,
scanwrite,
scandata,
phasecounterselect,
phaseupdown,
phasestep,
configupdate,
fbmimicbidir,
clk,
extclk,
clkbad,
enable0,
enable1,
activeclock,
clkloss,
locked,
scandataout,
scandone,
sclkout0,
sclkout1,
phasedone,
vcooverrange,
vcounderrange,
fbout,
fref,
icdrclk,
c0,
c1,
c2,
c3,
c4);
parameter intended_device_family = "MAX 10";
parameter operation_mode = "NORMAL";
parameter pll_type = "AUTO";
parameter qualify_conf_done = "OFF";
parameter compensate_clock = "CLK0";
parameter scan_chain = "LONG";
parameter primary_clock = "inclk0";
parameter inclk0_input_frequency = 1000;
parameter inclk1_input_frequency = 0;
parameter gate_lock_signal = "NO";
parameter gate_lock_counter = 0;
parameter lock_high = 1;
parameter lock_low = 0;
parameter valid_lock_multiplier = 1;
parameter invalid_lock_multiplier = 5;
parameter switch_over_type = "AUTO";
parameter switch_over_on_lossclk = "OFF" ;
parameter switch_over_on_gated_lock = "OFF" ;
parameter enable_switch_over_counter = "OFF";
parameter switch_over_counter = 0;
parameter feedback_source = "EXTCLK0" ;
parameter bandwidth = 0;
parameter bandwidth_type = "UNUSED";
parameter lpm_hint = "UNUSED";
parameter spread_frequency = 0;
parameter down_spread = "0.0";
parameter self_reset_on_gated_loss_lock = "OFF";
parameter self_reset_on_loss_lock = "OFF";
parameter lock_window_ui = "0.05";
parameter width_clock = 6;
parameter width_phasecounterselect = 4;
parameter charge_pump_current_bits = 9999;
parameter loop_filter_c_bits = 9999;
parameter loop_filter_r_bits = 9999;
parameter scan_chain_mif_file = "UNUSED";
parameter clk9_multiply_by = 1;
parameter clk8_multiply_by = 1;
parameter clk7_multiply_by = 1;
parameter clk6_multiply_by = 1;
parameter clk5_multiply_by = 1;
parameter clk4_multiply_by = 1;
parameter clk3_multiply_by = 1;
parameter clk2_multiply_by = 1;
parameter clk1_multiply_by = 1;
parameter clk0_multiply_by = 1;
parameter clk9_divide_by = 1;
parameter clk8_divide_by = 1;
parameter clk7_divide_by = 1;
parameter clk6_divide_by = 1;
parameter clk5_divide_by = 1;
parameter clk4_divide_by = 1;
parameter clk3_divide_by = 1;
parameter clk2_divide_by = 1;
parameter clk1_divide_by = 1;
parameter clk0_divide_by = 1;
parameter clk9_phase_shift = "0";
parameter clk8_phase_shift = "0";
parameter clk7_phase_shift = "0";
parameter clk6_phase_shift = "0";
parameter clk5_phase_shift = "0";
parameter clk4_phase_shift = "0";
parameter clk3_phase_shift = "0";
parameter clk2_phase_shift = "0";
parameter clk1_phase_shift = "0";
parameter clk0_phase_shift = "0";
parameter clk9_duty_cycle = 50;
parameter clk8_duty_cycle = 50;
parameter clk7_duty_cycle = 50;
parameter clk6_duty_cycle = 50;
parameter clk5_duty_cycle = 50;
parameter clk4_duty_cycle = 50;
parameter clk3_duty_cycle = 50;
parameter clk2_duty_cycle = 50;
parameter clk1_duty_cycle = 50;
parameter clk0_duty_cycle = 50;
parameter clk9_use_even_counter_mode = "OFF";
parameter clk8_use_even_counter_mode = "OFF";
parameter clk7_use_even_counter_mode = "OFF";
parameter clk6_use_even_counter_mode = "OFF";
parameter clk5_use_even_counter_mode = "OFF";
parameter clk4_use_even_counter_mode = "OFF";
parameter clk3_use_even_counter_mode = "OFF";
parameter clk2_use_even_counter_mode = "OFF";
parameter clk1_use_even_counter_mode = "OFF";
parameter clk0_use_even_counter_mode = "OFF";
parameter clk9_use_even_counter_value = "OFF";
parameter clk8_use_even_counter_value = "OFF";
parameter clk7_use_even_counter_value = "OFF";
parameter clk6_use_even_counter_value = "OFF";
parameter clk5_use_even_counter_value = "OFF";
parameter clk4_use_even_counter_value = "OFF";
parameter clk3_use_even_counter_value = "OFF";
parameter clk2_use_even_counter_value = "OFF";
parameter clk1_use_even_counter_value = "OFF";
parameter clk0_use_even_counter_value = "OFF";
parameter clk2_output_frequency = 0;
parameter clk1_output_frequency = 0;
parameter clk0_output_frequency = 0;
parameter vco_min = 0;
parameter vco_max = 0;
parameter vco_center = 0;
parameter pfd_min = 0;
parameter pfd_max = 0;
parameter m_initial = 1;
parameter m = 0;
parameter n = 1;
parameter m2 = 1;
parameter n2 = 1;
parameter ss = 0;
parameter l0_high = 1;
parameter l1_high = 1;
parameter g0_high = 1;
parameter g1_high = 1;
parameter g2_high = 1;
parameter g3_high = 1;
parameter e0_high = 1;
parameter e1_high = 1;
parameter e2_high = 1;
parameter e3_high = 1;
parameter l0_low = 1;
parameter l1_low = 1;
parameter g0_low = 1;
parameter g1_low = 1;
parameter g2_low = 1;
parameter g3_low = 1;
parameter e0_low = 1;
parameter e1_low = 1;
parameter e2_low = 1;
parameter e3_low = 1;
parameter l0_initial = 1;
parameter l1_initial = 1;
parameter g0_initial = 1;
parameter g1_initial = 1;
parameter g2_initial = 1;
parameter g3_initial = 1;
parameter e0_initial = 1;
parameter e1_initial = 1;
parameter e2_initial = 1;
parameter e3_initial = 1;
parameter l0_mode = "bypass";
parameter l1_mode = "bypass";
parameter g0_mode = "bypass";
parameter g1_mode = "bypass";
parameter g2_mode = "bypass";
parameter g3_mode = "bypass";
parameter e0_mode = "bypass";
parameter e1_mode = "bypass";
parameter e2_mode = "bypass";
parameter e3_mode = "bypass";
parameter l0_ph = 0;
parameter l1_ph = 0;
parameter g0_ph = 0;
parameter g1_ph = 0;
parameter g2_ph = 0;
parameter g3_ph = 0;
parameter e0_ph = 0;
parameter e1_ph = 0;
parameter e2_ph = 0;
parameter e3_ph = 0;
parameter m_ph = 0;
parameter l0_time_delay = 0;
parameter l1_time_delay = 0;
parameter g0_time_delay = 0;
parameter g1_time_delay = 0;
parameter g2_time_delay = 0;
parameter g3_time_delay = 0;
parameter e0_time_delay = 0;
parameter e1_time_delay = 0;
parameter e2_time_delay = 0;
parameter e3_time_delay = 0;
parameter m_time_delay = 0;
parameter n_time_delay = 0;
parameter extclk3_counter = "e3" ;
parameter extclk2_counter = "e2" ;
parameter extclk1_counter = "e1" ;
parameter extclk0_counter = "e0" ;
parameter clk9_counter = "c9" ;
parameter clk8_counter = "c8" ;
parameter clk7_counter = "c7" ;
parameter clk6_counter = "c6" ;
parameter clk5_counter = "l1" ;
parameter clk4_counter = "l0" ;
parameter clk3_counter = "g3" ;
parameter clk2_counter = "g2" ;
parameter clk1_counter = "g1" ;
parameter clk0_counter = "g0" ;
parameter enable0_counter = "l0";
parameter enable1_counter = "l0";
parameter charge_pump_current = 2;
parameter loop_filter_r = "1.0";
parameter loop_filter_c = 5;
parameter vco_post_scale = 0;
parameter vco_frequency_control = "AUTO";
parameter vco_phase_shift_step = 0;
parameter lpm_type = "altpll";
parameter port_clkena0 = "PORT_CONNECTIVITY";
parameter port_clkena1 = "PORT_CONNECTIVITY";
parameter port_clkena2 = "PORT_CONNECTIVITY";
parameter port_clkena3 = "PORT_CONNECTIVITY";
parameter port_clkena4 = "PORT_CONNECTIVITY";
parameter port_clkena5 = "PORT_CONNECTIVITY";
parameter port_extclkena0 = "PORT_CONNECTIVITY";
parameter port_extclkena1 = "PORT_CONNECTIVITY";
parameter port_extclkena2 = "PORT_CONNECTIVITY";
parameter port_extclkena3 = "PORT_CONNECTIVITY";
parameter port_extclk0 = "PORT_CONNECTIVITY";
parameter port_extclk1 = "PORT_CONNECTIVITY";
parameter port_extclk2 = "PORT_CONNECTIVITY";
parameter port_extclk3 = "PORT_CONNECTIVITY";
parameter port_clk0 = "PORT_CONNECTIVITY";
parameter port_clk1 = "PORT_CONNECTIVITY";
parameter port_clk2 = "PORT_CONNECTIVITY";
parameter port_clk3 = "PORT_CONNECTIVITY";
parameter port_clk4 = "PORT_CONNECTIVITY";
parameter port_clk5 = "PORT_CONNECTIVITY";
parameter port_clk6 = "PORT_CONNECTIVITY";
parameter port_clk7 = "PORT_CONNECTIVITY";
parameter port_clk8 = "PORT_CONNECTIVITY";
parameter port_clk9 = "PORT_CONNECTIVITY";
parameter port_scandata = "PORT_CONNECTIVITY";
parameter port_scandataout = "PORT_CONNECTIVITY";
parameter port_scandone = "PORT_CONNECTIVITY";
parameter port_sclkout1 = "PORT_CONNECTIVITY";
parameter port_sclkout0 = "PORT_CONNECTIVITY";
parameter port_clkbad0 = "PORT_CONNECTIVITY";
parameter port_clkbad1 = "PORT_CONNECTIVITY";
parameter port_activeclock = "PORT_CONNECTIVITY";
parameter port_clkloss = "PORT_CONNECTIVITY";
parameter port_inclk1 = "PORT_CONNECTIVITY";
parameter port_inclk0 = "PORT_CONNECTIVITY";
parameter port_fbin = "PORT_CONNECTIVITY";
parameter port_fbout = "PORT_CONNECTIVITY";
parameter port_pllena = "PORT_CONNECTIVITY";
parameter port_clkswitch = "PORT_CONNECTIVITY";
parameter port_areset = "PORT_CONNECTIVITY";
parameter port_pfdena = "PORT_CONNECTIVITY";
parameter port_scanclk = "PORT_CONNECTIVITY";
parameter port_scanaclr = "PORT_CONNECTIVITY";
parameter port_scanread = "PORT_CONNECTIVITY";
parameter port_scanwrite = "PORT_CONNECTIVITY";
parameter port_enable0 = "PORT_CONNECTIVITY";
parameter port_enable1 = "PORT_CONNECTIVITY";
parameter port_locked = "PORT_CONNECTIVITY";
parameter port_configupdate = "PORT_CONNECTIVITY";
parameter port_phasecounterselect = "PORT_CONNECTIVITY";
parameter port_phasedone = "PORT_CONNECTIVITY";
parameter port_phasestep = "PORT_CONNECTIVITY";
parameter port_phaseupdown = "PORT_CONNECTIVITY";
parameter port_vcooverrange = "PORT_CONNECTIVITY";
parameter port_vcounderrange = "PORT_CONNECTIVITY";
parameter port_scanclkena = "PORT_CONNECTIVITY";
parameter using_fbmimicbidir_port = "ON";
input [1:0] inclk;
input fbin;
input pllena;
input clkswitch;
input areset;
input pfdena;
input clkena;
input extclkena;
input scanclk;
input scanaclr;
input scanclkena;
input scanread;
input scanwrite;
input scandata;
input phasecounterselect;
input phaseupdown;
input phasestep;
input configupdate;
inout fbmimicbidir;
output [width_clock-1:0] clk;
output [3:0] extclk;
output [1:0] clkbad;
output enable0;
output enable1;
output activeclock;
output clkloss;
output locked;
output scandataout;
output scandone;
output sclkout0;
output sclkout1;
output phasedone;
output vcooverrange;
output vcounderrange;
output fbout;
output fref;
output icdrclk;
output c0, c1, c2, c3, c4;
endmodule // altpll
`endif

33
techlibs/intel/common/brams.txt Executable file
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bram $__M9K_ALTSYNCRAM_SINGLEPORT_FULL
init 1
abits 13 @M1
dbits 1 @M1
abits 12 @M2
dbits 2 @M2
abits 11 @M3
dbits 4 @M3
abits 10 @M4
dbits 8 @M4
abits 10 @M5
dbits 9 @M5
abits 9 @M6
dbits 16 @M6
abits 9 @M7
dbits 18 @M7
abits 8 @M8
dbits 32 @M8
abits 8 @M9
dbits 36 @M9
groups 2
ports 1 1
wrmode 0 1
enable 1 1
transp 0 0
clocks 2 3
clkpol 2 3
endbram
match $__M9K_ALTSYNCRAM_SINGLEPORT_FULL
min efficiency 2
make_transp
endmatch

95
techlibs/intel/common/brams_map.v Executable file
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module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 8;
parameter CFG_DBITS = 36;
parameter ABITS = "1";
parameter DBITS = "1";
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
input CLK2;
input CLK3;
//Read data
output [CFG_DBITS-1:0] A1DATA;
input [CFG_ABITS-1:0] A1ADDR;
input A1EN;
//Write data
output [CFG_DBITS-1:0] B1DATA;
input [CFG_ABITS-1:0] B1ADDR;
input B1EN;
wire [CFG_DBITS-1:0] B1DATA_t;
localparam MODE = CFG_DBITS == 1 ? 1:
CFG_DBITS == 2 ? 2:
CFG_DBITS == 4 ? 3:
CFG_DBITS == 8 ? 4:
CFG_DBITS == 9 ? 5:
CFG_DBITS == 16 ? 6:
CFG_DBITS == 18 ? 7:
CFG_DBITS == 32 ? 8:
CFG_DBITS == 36 ? 9:
'bx;
localparam NUMWORDS = CFG_DBITS == 1 ? "8192":
CFG_DBITS == 2 ? "4096":
CFG_DBITS == 4 ? "2048":
CFG_DBITS == 8 ? "1024":
CFG_DBITS == 9 ? "1024":
CFG_DBITS == 16 ? "512":
CFG_DBITS == 18 ? "512":
CFG_DBITS == 32 ? "256":
CFG_DBITS == 36 ? "256":
'bx;
/* Killing some stupid warnings and assignations*/
/* generate
if( MODE == 1 ) begin
assign B1DATA_t = ({34{1'b0},B1DATA[0]});
end
endgenerate*/
altsyncram #(.clock_enable_input_b ("ALTERNATE" ),
.clock_enable_input_a ("ALTERNATE" ),
.clock_enable_output_b ("NORMAL" ),
.clock_enable_output_a ("NORMAL" ),
.wrcontrol_aclr_a ("NONE" ),
.indata_aclr_a ("NONE" ),
.address_aclr_a ("NONE" ),
.outdata_aclr_a ("NONE" ),
.outdata_reg_a ("UNREGISTERED"),
.operation_mode ("SINGLE_PORT" ),
.intended_device_family ("CYCLONE IVE" ),
.outdata_reg_a ("UNREGISTERED"),
.lpm_type ("altsyncram" ),
.init_type ("unused" ),
.ram_block_type ("AUTO" ),
.numwords_b ( NUMWORDS ),
.numwords_a ( NUMWORDS ),
.widthad_b ( CFG_ABITS ),
.width_b ( CFG_DBITS ),
.widthad_a ( CFG_ABITS ),
.width_a ( CFG_DBITS )
) _TECHMAP_REPLACE_ (
.data_a(B1DATA),
.address_a(B1ADDR),
.wren_a(B1EN),
.rden_a(A1EN),
.q_a(A1DATA),
.data_b(1'b0),
.address_b(0),
.wren_b(1'b0),
.rden_b(1'b0),
.q_b(1'b0),
.clock0(CLK2),
.clock1(1'b1), // Unused in single port mode
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
.aclr0(1'b0),
.aclr1(1'b0),
.addressstall_a(1'b0),
.addressstall_b(1'b0));
endmodule

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* blackbox *)
module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wren_b, rden_b,
q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1,
addressstall_a, addressstall_b);
parameter clock_enable_input_b = "ALTERNATE";
parameter clock_enable_input_a = "ALTERNATE";
parameter clock_enable_output_b = "NORMAL";
parameter clock_enable_output_a = "NORMAL";
parameter wrcontrol_aclr_a = "NONE";
parameter indata_aclr_a = "NONE";
parameter address_aclr_a = "NONE";
parameter outdata_aclr_a = "NONE";
parameter outdata_reg_a = "UNREGISTERED";
parameter operation_mode = "SINGLE_PORT";
parameter intended_device_family = "MAX 10 FPGA";
parameter outdata_reg_a = "UNREGISTERED";
parameter lpm_type = "altsyncram";
parameter init_type = "unused";
parameter ram_block_type = "AUTO";
parameter numwords_b = 0;
parameter numwords_a = 0;
parameter widthad_b = 1;
parameter width_b = 1;
parameter widthad_a = 1;
parameter width_a = 1;
// Port A declarations
output [35:0] q_a;
input [35:0] data_a;
input [7:0] address_a;
input wren_a;
input rden_a;
// Port B declarations
output [35:0] q_b;
input [35:0] data_b;
input [7:0] address_b;
input wren_b;
input rden_b;
// Control signals
input clock0, clock1;
input clocken0, clocken1, clocken2, clocken3;
input aclr0, aclr1;
input addressstall_a;
input addressstall_b;
// TODO: Implement the correct simulation model
endmodule // altsyncram

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// NOTE: This is still WIP.
(* techmap_celltype = "$alu" *)
/* Uncomment this for LCU????
module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
//output [Y_WIDTH-1:0] CO;
output CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
wire [Y_WIDTH+1:0] C = {COx, CI};
/* Start implementation */
//cycloneiv_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
/*
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
if(i==Y_WIDTH-1)
(* keep *) cycloneiv_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(CO), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH]));
//assign CO = COx[Y_WIDTH];
else
cycloneiv_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1]));
end: slice
endgenerate
/* End implementation */
/*assign X = AA ^ BB;
endmodule*/
module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
output [Y_WIDTH:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH < 6;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH:0] C = {CO, CI};
cycloneiv_lcell_comb #(.lut_mask(16'b0110_0110_1000_1000), .sum_lutc_input("cin")) carry_start (.cout(CO[0]), .dataa(BB[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
genvar i;
generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice
cycloneiv_lcell_comb #(.lut_mask(16'b0101_1010_0101_0000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(CO[i]), .dataa(BB[i]), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[i]));
end endgenerate
assign X = AA ^ BB;
endmodule

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// Normal mode DFF negedge clk, negedge reset
module \$_DFF_N_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Normal mode DFF
module \$_DFF_P_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active Low Reset DFF
module \$_DFF_PN0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active High Reset DFF
module \$_DFF_PP0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
wire R_i = ~ R;
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
module \$__DFFE_PP0 (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
wire E_i = ~ E;
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
endmodule
// Input buffer map
module \$__inpad (input I, output O);
cycloneiv_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
endmodule
// Output buffer map
module \$__outpad (input I, output O);
cycloneiv_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
endmodule
// LUT Map
/* 0 -> datac
1 -> cin */
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else
if (WIDTH == 2) begin
cycloneiv_lcell_comb #(.lut_mask({4{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1));
end else
if(WIDTH == 3) begin
cycloneiv_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));
end else
if(WIDTH == 4) begin
cycloneiv_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3]));
end else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule //

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module VCC (output V);
assign V = 1'b1;
endmodule // VCC
module GND (output G);
assign G = 1'b0;
endmodule // GND
/* Altera Cyclone IV (GX) devices Input Buffer Primitive */
module cycloneiv_io_ibuf
(output o, input i, input ibar);
assign ibar = ibar;
assign o = i;
endmodule // fiftyfivenm_io_ibuf
/* Altera Cyclone IV (GX) devices Output Buffer Primitive */
module cycloneiv_io_obuf
(output o, input i, input oe);
assign o = i;
assign oe = oe;
endmodule // fiftyfivenm_io_obuf
/* Altera Cyclone IV (GX) 4-input non-fracturable LUT Primitive */
module cycloneiv_lcell_comb
(output combout, cout,
input dataa, datab, datac, datad, cin);
/* Internal parameters which define the behaviour
of the LUT primitive.
lut_mask define the lut function, can be expressed in 16-digit bin or hex.
sum_lutc_input define the type of LUT (combinational | arithmetic).
dont_touch for retiming || carry options.
lpm_type for WYSIWYG */
parameter lut_mask = 16'hFFFF;
parameter dont_touch = "off";
parameter lpm_type = "cycloneiv_lcell_comb";
parameter sum_lutc_input = "datac";
reg [1:0] lut_type;
reg cout_rt;
reg combout_rt;
wire dataa_w;
wire datab_w;
wire datac_w;
wire datad_w;
wire cin_w;
assign dataa_w = dataa;
assign datab_w = datab;
assign datac_w = datac;
assign datad_w = datad;
function lut_data;
input [15:0] mask;
input dataa, datab, datac, datad;
reg [7:0] s3;
reg [3:0] s2;
reg [1:0] s1;
begin
s3 = datad ? mask[15:8] : mask[7:0];
s2 = datac ? s3[7:4] : s3[3:0];
s1 = datab ? s2[3:2] : s2[1:0];
lut_data = dataa ? s1[1] : s1[0];
end
endfunction
initial begin
if (sum_lutc_input == "datac") lut_type = 0;
else
if (sum_lutc_input == "cin") lut_type = 1;
else begin
$error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input);
$finish();
end
end
always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
if (lut_type == 0) begin // logic function
combout_rt = lut_data(lut_mask, dataa_w, datab_w,
datac_w, datad_w);
end
else if (lut_type == 1) begin // arithmetic function
combout_rt = lut_data(lut_mask, dataa_w, datab_w,
cin_w, datad_w);
end
cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0);
end
assign combout = combout_rt & 1'b1;
assign cout = cout_rt & 1'b1;
endmodule // cycloneiv_lcell_comb
/* Altera D Flip-Flop Primitive */
module dffeas
(output q,
input d, clk, clrn, prn, ena,
input asdata, aload, sclr, sload);
// Timing simulation is not covered
parameter power_up="dontcare";
parameter is_wysiwyg="false";
reg q_tmp;
wire reset;
reg [7:0] debug_net;
assign reset = (prn && sclr && ~clrn && ena);
assign q = q_tmp & 1'b1;
always @(posedge clk, posedge aload) begin
if(reset) q_tmp <= 0;
else q_tmp <= d;
end
assign q = q_tmp;
endmodule // dffeas
/* Cyclone IV GX altpll clearbox model */
(* blackbox *)
module cycloneiv_pll
(inclk,
fbin,
fbout,
clkswitch,
areset,
pfdena,
scanclk,
scandata,
scanclkena,
configupdate,
clk,
phasecounterselect,
phaseupdown,
phasestep,
clkbad,
activeclock,
locked,
scandataout,
scandone,
phasedone,
vcooverrange,
vcounderrange,
fref,
icdrclk);
parameter operation_mode = "normal";
parameter pll_type = "auto";
parameter compensate_clock = "clock0";
parameter inclk0_input_frequency = 0;
parameter inclk1_input_frequency = 0;
parameter self_reset_on_loss_lock = "off";
parameter switch_over_type = "auto";
parameter switch_over_counter = 1;
parameter enable_switch_over_counter = "off";
parameter bandwidth = 0;
parameter bandwidth_type = "auto";
parameter use_dc_coupling = "false";
parameter lock_high = 0;
parameter lock_low = 0;
parameter lock_window_ui = "0.05";
parameter test_bypass_lock_detect = "off";
parameter clk0_output_frequency = 0;
parameter clk0_multiply_by = 0;
parameter clk0_divide_by = 0;
parameter clk0_phase_shift = "0";
parameter clk0_duty_cycle = 50;
parameter clk1_output_frequency = 0;
parameter clk1_multiply_by = 0;
parameter clk1_divide_by = 0;
parameter clk1_phase_shift = "0";
parameter clk1_duty_cycle = 50;
parameter clk2_output_frequency = 0;
parameter clk2_multiply_by = 0;
parameter clk2_divide_by = 0;
parameter clk2_phase_shift = "0";
parameter clk2_duty_cycle = 50;
parameter clk3_output_frequency = 0;
parameter clk3_multiply_by = 0;
parameter clk3_divide_by = 0;
parameter clk3_phase_shift = "0";
parameter clk3_duty_cycle = 50;
parameter clk4_output_frequency = 0;
parameter clk4_multiply_by = 0;
parameter clk4_divide_by = 0;
parameter clk4_phase_shift = "0";
parameter clk4_duty_cycle = 50;
parameter pfd_min = 0;
parameter pfd_max = 0;
parameter vco_min = 0;
parameter vco_max = 0;
parameter vco_center = 0;
// Advanced user parameters
parameter m_initial = 1;
parameter m = 0;
parameter n = 1;
parameter c0_high = 1;
parameter c0_low = 1;
parameter c0_initial = 1;
parameter c0_mode = "bypass";
parameter c0_ph = 0;
parameter c1_high = 1;
parameter c1_low = 1;
parameter c1_initial = 1;
parameter c1_mode = "bypass";
parameter c1_ph = 0;
parameter c2_high = 1;
parameter c2_low = 1;
parameter c2_initial = 1;
parameter c2_mode = "bypass";
parameter c2_ph = 0;
parameter c3_high = 1;
parameter c3_low = 1;
parameter c3_initial = 1;
parameter c3_mode = "bypass";
parameter c3_ph = 0;
parameter c4_high = 1;
parameter c4_low = 1;
parameter c4_initial = 1;
parameter c4_mode = "bypass";
parameter c4_ph = 0;
parameter m_ph = 0;
parameter clk0_counter = "unused";
parameter clk1_counter = "unused";
parameter clk2_counter = "unused";
parameter clk3_counter = "unused";
parameter clk4_counter = "unused";
parameter c1_use_casc_in = "off";
parameter c2_use_casc_in = "off";
parameter c3_use_casc_in = "off";
parameter c4_use_casc_in = "off";
parameter m_test_source = -1;
parameter c0_test_source = -1;
parameter c1_test_source = -1;
parameter c2_test_source = -1;
parameter c3_test_source = -1;
parameter c4_test_source = -1;
parameter vco_multiply_by = 0;
parameter vco_divide_by = 0;
parameter vco_post_scale = 1;
parameter vco_frequency_control = "auto";
parameter vco_phase_shift_step = 0;
parameter charge_pump_current = 10;
parameter loop_filter_r = "1.0";
parameter loop_filter_c = 0;
parameter pll_compensation_delay = 0;
parameter lpm_type = "cycloneiv_pll";
parameter phase_counter_select_width = 3;
input [1:0] inclk;
input fbin;
input clkswitch;
input areset;
input pfdena;
input [phase_counter_select_width - 1:0] phasecounterselect;
input phaseupdown;
input phasestep;
input scanclk;
input scanclkena;
input scandata;
input configupdate;
output [4:0] clk;
output [1:0] clkbad;
output activeclock;
output locked;
output scandataout;
output scandone;
output fbout;
output phasedone;
output vcooverrange;
output vcounderrange;
output fref;
output icdrclk;
endmodule // cycloneive_pll

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
output [Y_WIDTH:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH < 5;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH:0] C = {CO, CI};
cycloneive_lcell_comb #(.lut_mask(16'b0110_0110_1000_1000), .sum_lutc_input("cin")) carry_start (.cout(CO[0]), .dataa(BB[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
genvar i;
generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice
cycloneive_lcell_comb #(.lut_mask(16'b0101_1010_0101_0000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(CO[i]), .dataa(BB[i]), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[i]));
end endgenerate
assign X = AA ^ BB;
endmodule

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// Normal mode DFF negedge clk, negedge reset
module \$_DFF_N_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Normal mode DFF
module \$_DFF_P_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active Low Reset DFF
module \$_DFF_PN0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active High Reset DFF
module \$_DFF_PP0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
wire R_i = ~ R;
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
module \$__DFFE_PP0 (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
wire E_i = ~ E;
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
endmodule
// Input buffer map
module \$__inpad (input I, output O);
cycloneive_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
endmodule
// Output buffer map
module \$__outpad (input I, output O);
cycloneive_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
endmodule
// LUT Map
/* 0 -> datac
1 -> cin */
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else
if (WIDTH == 2) begin
cycloneive_lcell_comb #(.lut_mask({4{LUT}}),
.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(1'b1),
.datad(1'b1));
end else
if(WIDTH == 3) begin
cycloneive_lcell_comb #(.lut_mask({2{LUT}}),
.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(A[2]),
.datad(1'b1));
end else
if(WIDTH == 4) begin
cycloneive_lcell_comb #(.lut_mask(LUT),
.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(A[2]),
.datad(A[3]));
end else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module VCC (output V);
assign V = 1'b1;
endmodule // VCC
module GND (output G);
assign G = 1'b0;
endmodule // GND
/* Altera Cyclone IV (E) devices Input Buffer Primitive */
module cycloneive_io_ibuf
(output o, input i, input ibar);
assign ibar = ibar;
assign o = i;
endmodule // fiftyfivenm_io_ibuf
/* Altera Cyclone IV (E) devices Output Buffer Primitive */
module cycloneive_io_obuf
(output o, input i, input oe);
assign o = i;
assign oe = oe;
endmodule // fiftyfivenm_io_obuf
/* Altera Cyclone IV (E) 4-input non-fracturable LUT Primitive */
module cycloneive_lcell_comb
(output combout, cout,
input dataa, datab, datac, datad, cin);
/* Internal parameters which define the behaviour
of the LUT primitive.
lut_mask define the lut function, can be expressed in 16-digit bin or hex.
sum_lutc_input define the type of LUT (combinational | arithmetic).
dont_touch for retiming || carry options.
lpm_type for WYSIWYG */
parameter lut_mask = 16'hFFFF;
parameter dont_touch = "off";
parameter lpm_type = "cycloneive_lcell_comb";
parameter sum_lutc_input = "datac";
reg [1:0] lut_type;
reg cout_rt;
reg combout_rt;
wire dataa_w;
wire datab_w;
wire datac_w;
wire datad_w;
wire cin_w;
assign dataa_w = dataa;
assign datab_w = datab;
assign datac_w = datac;
assign datad_w = datad;
function lut_data;
input [15:0] mask;
input dataa, datab, datac, datad;
reg [7:0] s3;
reg [3:0] s2;
reg [1:0] s1;
begin
s3 = datad ? mask[15:8] : mask[7:0];
s2 = datac ? s3[7:4] : s3[3:0];
s1 = datab ? s2[3:2] : s2[1:0];
lut_data = dataa ? s1[1] : s1[0];
end
endfunction
initial begin
if (sum_lutc_input == "datac") lut_type = 0;
else
if (sum_lutc_input == "cin") lut_type = 1;
else begin
$error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input);
$finish();
end
end
always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
if (lut_type == 0) begin // logic function
combout_rt = lut_data(lut_mask, dataa_w, datab_w,
datac_w, datad_w);
end
else if (lut_type == 1) begin // arithmetic function
combout_rt = lut_data(lut_mask, dataa_w, datab_w,
cin_w, datad_w);
end
cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0);
end
assign combout = combout_rt & 1'b1;
assign cout = cout_rt & 1'b1;
endmodule // cycloneive_lcell_comb
/* Altera D Flip-Flop Primitive */
module dffeas
(output q,
input d, clk, clrn, prn, ena,
input asdata, aload, sclr, sload);
// Timing simulation is not covered
parameter power_up="dontcare";
parameter is_wysiwyg="false";
reg q_tmp;
wire reset;
reg [7:0] debug_net;
assign reset = (prn && sclr && ~clrn && ena);
assign q = q_tmp & 1'b1;
always @(posedge clk, posedge aload) begin
if(reset) q_tmp <= 0;
else q_tmp <= d;
end
assign q = q_tmp;
endmodule // dffeas
/* Cyclone IV E altpll clearbox model */
(* blackbox *)
module cycloneive_pll
(inclk,
fbin,
fbout,
clkswitch,
areset,
pfdena,
scanclk,
scandata,
scanclkena,
configupdate,
clk,
phasecounterselect,
phaseupdown,
phasestep,
clkbad,
activeclock,
locked,
scandataout,
scandone,
phasedone,
vcooverrange,
vcounderrange);
parameter operation_mode = "normal";
parameter pll_type = "auto";
parameter compensate_clock = "clock0";
parameter inclk0_input_frequency = 0;
parameter inclk1_input_frequency = 0;
parameter self_reset_on_loss_lock = "off";
parameter switch_over_type = "auto";
parameter switch_over_counter = 1;
parameter enable_switch_over_counter = "off";
parameter bandwidth = 0;
parameter bandwidth_type = "auto";
parameter use_dc_coupling = "false";
parameter lock_high = 0;
parameter lock_low = 0;
parameter lock_window_ui = "0.05";
parameter test_bypass_lock_detect = "off";
parameter clk0_output_frequency = 0;
parameter clk0_multiply_by = 0;
parameter clk0_divide_by = 0;
parameter clk0_phase_shift = "0";
parameter clk0_duty_cycle = 50;
parameter clk1_output_frequency = 0;
parameter clk1_multiply_by = 0;
parameter clk1_divide_by = 0;
parameter clk1_phase_shift = "0";
parameter clk1_duty_cycle = 50;
parameter clk2_output_frequency = 0;
parameter clk2_multiply_by = 0;
parameter clk2_divide_by = 0;
parameter clk2_phase_shift = "0";
parameter clk2_duty_cycle = 50;
parameter clk3_output_frequency = 0;
parameter clk3_multiply_by = 0;
parameter clk3_divide_by = 0;
parameter clk3_phase_shift = "0";
parameter clk3_duty_cycle = 50;
parameter clk4_output_frequency = 0;
parameter clk4_multiply_by = 0;
parameter clk4_divide_by = 0;
parameter clk4_phase_shift = "0";
parameter clk4_duty_cycle = 50;
parameter pfd_min = 0;
parameter pfd_max = 0;
parameter vco_min = 0;
parameter vco_max = 0;
parameter vco_center = 0;
// Advanced user parameters
parameter m_initial = 1;
parameter m = 0;
parameter n = 1;
parameter c0_high = 1;
parameter c0_low = 1;
parameter c0_initial = 1;
parameter c0_mode = "bypass";
parameter c0_ph = 0;
parameter c1_high = 1;
parameter c1_low = 1;
parameter c1_initial = 1;
parameter c1_mode = "bypass";
parameter c1_ph = 0;
parameter c2_high = 1;
parameter c2_low = 1;
parameter c2_initial = 1;
parameter c2_mode = "bypass";
parameter c2_ph = 0;
parameter c3_high = 1;
parameter c3_low = 1;
parameter c3_initial = 1;
parameter c3_mode = "bypass";
parameter c3_ph = 0;
parameter c4_high = 1;
parameter c4_low = 1;
parameter c4_initial = 1;
parameter c4_mode = "bypass";
parameter c4_ph = 0;
parameter m_ph = 0;
parameter clk0_counter = "unused";
parameter clk1_counter = "unused";
parameter clk2_counter = "unused";
parameter clk3_counter = "unused";
parameter clk4_counter = "unused";
parameter c1_use_casc_in = "off";
parameter c2_use_casc_in = "off";
parameter c3_use_casc_in = "off";
parameter c4_use_casc_in = "off";
parameter m_test_source = -1;
parameter c0_test_source = -1;
parameter c1_test_source = -1;
parameter c2_test_source = -1;
parameter c3_test_source = -1;
parameter c4_test_source = -1;
parameter vco_multiply_by = 0;
parameter vco_divide_by = 0;
parameter vco_post_scale = 1;
parameter vco_frequency_control = "auto";
parameter vco_phase_shift_step = 0;
parameter charge_pump_current = 10;
parameter loop_filter_r = "1.0";
parameter loop_filter_c = 0;
parameter pll_compensation_delay = 0;
parameter lpm_type = "cycloneive_pll";
parameter phase_counter_select_width = 3;
input [1:0] inclk;
input fbin;
input clkswitch;
input areset;
input pfdena;
input [phase_counter_select_width - 1:0] phasecounterselect;
input phaseupdown;
input phasestep;
input scanclk;
input scanclkena;
input scandata;
input configupdate;
output [4:0] clk;
output [1:0] clkbad;
output activeclock;
output locked;
output scandataout;
output scandone;
output fbout;
output phasedone;
output vcooverrange;
output vcounderrange;
endmodule // cycloneive_pll

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// NOTE: This is still WIP.
(* techmap_celltype = "$alu" *)
module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
//output [Y_WIDTH-1:0] CO;
output CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
wire [Y_WIDTH+1:0] C = {COx, CI};
/* Start implementation */
(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
if(i==Y_WIDTH-1) begin
(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH]));
assign CO = COx[Y_WIDTH];
end
else
fiftyfivenm_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1]));
end: slice
endgenerate
/* End implementation */
assign X = AA ^ BB;
endmodule

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// Normal mode DFF negedge clk, negedge reset
module \$_DFF_N_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Normal mode DFF
module \$_DFF_P_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active Low Reset DFF
module \$_DFF_PN0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active High Reset DFF
module \$_DFF_PP0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
wire R_i = ~ R;
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
module \$__DFFE_PP0 (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
wire E_i = ~ E;
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
endmodule
// Input buffer map
module \$__inpad (input I, output O);
cyclonev_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
endmodule
// Output buffer map
module \$__outpad (input I, output O);
cyclonev_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
endmodule
// LUT Map
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end
else
if (WIDTH == 2) begin
cyclonev_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off"))
_TECHMAP_REPLACE_
(.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(1'b1),
.datad(1'b1),
.datae(1'b1),
.dataf(1'b1),
.datag(1'b1));
end
else
if(WIDTH == 3) begin
cyclonev_lcell_comb #(.lut_mask({8{LUT}}), .shared_arith("off"), .extended_lut("off"))
_TECHMAP_REPLACE_
(.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(A[2]),
.datad(1'b1),
.datae(1'b1),
.dataf(1'b1),
.datag(1'b1));
end
else
if(WIDTH == 4) begin
cyclonev_lcell_comb #(.lut_mask({4{LUT}}), .shared_arith("off"), .extended_lut("off"))
_TECHMAP_REPLACE_
(.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(A[2]),
.datad(A[3]),
.datae(1'b1),
.dataf(1'b1),
.datag(1'b1));
end
else
if(WIDTH == 5) begin
cyclonev_lcell_comb #(.lut_mask({2{LUT}}), .shared_arith("off"), .extended_lut("off"))
_TECHMAP_REPLACE_
(.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(A[2]),
.datad(A[3]),
.datae(A[4]),
.dataf(1'b1),
.datag(1'b1));
end
else
if(WIDTH == 6) begin
cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off"))
_TECHMAP_REPLACE_
(.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(A[2]),
.datad(A[3]),
.datae(A[4]),
.dataf(A[5]),
.datag(1'b1));
end
else
if(WIDTH == 7) begin
cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off"))
_TECHMAP_REPLACE_
(.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(A[2]),
.datad(A[3]),
.datae(A[4]),
.dataf(A[5]),
.datag(A[6]));
end
else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule // lut

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module VCC (output V);
assign V = 1'b1;
endmodule // VCC
module GND (output G);
assign G = 1'b0;
endmodule // GND
/* Altera Cyclone V devices Input Buffer Primitive */
module cyclonev_io_ibuf
(output o, input i, input ibar);
assign ibar = ibar;
assign o = i;
endmodule // cyclonev_io_ibuf
/* Altera Cyclone V devices Output Buffer Primitive */
module cyclonev_io_obuf
(output o, input i, input oe);
assign o = i;
assign oe = oe;
endmodule // cyclonev_io_obuf
/* Altera Cyclone V LUT Primitive */
module cyclonev_lcell_comb
(output combout, cout, sumout, shareout,
input dataa, datab, datac, datad,
input datae, dataf, datag, cin,
input sharein);
parameter lut_mask = 64'hFFFFFFFFFFFFFFFF;
parameter dont_touch = "off";
parameter lpm_type = "cyclonev_lcell_comb";
parameter shared_arith = "off";
parameter extended_lut = "off";
// Internal variables
// Sub mask for fragmented LUTs
wire [15:0] mask_a, mask_b, mask_c, mask_d;
// Independant output for fragmented LUTs
wire output_0, output_1, output_2, output_3;
// Extended mode uses mux to define the output
wire mux_0, mux_1;
// Input for hold the shared LUT mode value
wire shared_lut_alm;
// Simulation model of 4-input LUT
function lut4;
input [15:0] mask;
input dataa, datab, datac, datad;
reg [7:0] s3;
reg [3:0] s2;
reg [1:0] s1;
begin
s3 = datad ? mask[15:8] : mask[7:0];
s2 = datac ? s3[7:4] : s3[3:0];
s1 = datab ? s2[3:2] : s2[1:0];
lut4 = dataa ? s1[1] : s1[0];
end
endfunction // lut4
// Simulation model of 5-input LUT
function lut5;
input [31:0] mask; // wp-01003.pdf, page 3: "a 5-LUT can be built with two 4-LUTs and a multiplexer.
input dataa, datab, datac, datad, datae;
reg upper_lut_value;
reg lower_lut_value;
begin
upper_lut_value = lut4(mask[31:16], dataa, datab, datac, datad);
lower_lut_value = lut4(mask[15:0], dataa, datab, datac, datad);
lut5 = (datae) ? upper_mask_value : lower_mask_value;
end
endfunction // lut5
// Simulation model of 6-input LUT
function lut6;
input [63:0] mask;
input dataa, datab, datac, datad, datae, dataf;
reg upper_lut_value;
reg lower_lut_value;
begin
upper_lut_value = lut5(mask[63:32], dataa, datab, datac, datad, datae);
lower_lut_value = lut5(mask[31:0], dataa, datab, datac, datad, datae);
lut6 = (dataf) ? upper_mask_value : lower_mask_value;
end
endfunction // lut6
assign {mask_a, mask_b, mask_c, mask_d} = {lut_mask[15:0], lut_mask[31:16], lut_mask[47:32], lut_mask[63:48]};
always @(*) begin
if(extended_lut == "on")
shared_lut_alm = datag;
else
shared_lut_alm = datac;
// Build the ALM behaviour
out_0 = lut4(mask_a, dataa, datab, datac, datad);
out_1 = lut4(mask_b, dataa, datab, shared_lut_alm, datad);
out_2 = lut4(mask_c, dataa, datab, datac, datad);
out_3 = lut4(mask_d, dataa, datab, shared_lut_alm, datad);
end
endmodule // cyclonev_lcell_comb
/* Altera D Flip-Flop Primitive */
module dffeas
(output q,
input d, clk, clrn, prn, ena,
input asdata, aload, sclr, sload);
// Timing simulation is not covered
parameter power_up="dontcare";
parameter is_wysiwyg="false";
reg q_tmp;
wire reset;
reg [7:0] debug_net;
assign reset = (prn && sclr && ~clrn && ena);
assign q = q_tmp & 1'b1;
always @(posedge clk, posedge aload) begin
if(reset) q_tmp <= 0;
else q_tmp <= d;
end
assign q = q_tmp;
endmodule // dffeas

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// NOTE: This is still WIP.
(* techmap_celltype = "$alu" *)
module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
//output [Y_WIDTH-1:0] CO;
output CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
wire [Y_WIDTH+1:0] C = {COx, CI};
/* Start implementation */
(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
if(i==Y_WIDTH-1) begin
(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH]));
assign CO = COx[Y_WIDTH];
end
else
fiftyfivenm_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1]));
end: slice
endgenerate
/* End implementation */
assign X = AA ^ BB;
endmodule

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// Normal mode DFF negedge clk, negedge reset
module \$_DFF_N_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Normal mode DFF
module \$_DFF_P_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active Low Reset DFF
module \$_DFF_PN0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active High Reset DFF
module \$_DFF_PP0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
wire R_i = ~ R;
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
module \$__DFFE_PP0 (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
wire E_i = ~ E;
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
endmodule
// Input buffer map
module \$__inpad (input I, output O);
fiftyfivenm_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
endmodule
// Output buffer map
module \$__outpad (input I, output O);
fiftyfivenm_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
endmodule
// LUT Map
/* 0 -> datac
1 -> cin */
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else
if (WIDTH == 2) begin
fiftyfivenm_lcell_comb #(.lut_mask({4{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1));
end else
if(WIDTH == 3) begin
fiftyfivenm_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));
end else
if(WIDTH == 4) begin
fiftyfivenm_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3]));
end else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule //

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module VCC (output V);
assign V = 1'b1;
endmodule // VCC
module GND (output G);
assign G = 1'b0;
endmodule // GND
/* Altera MAX10 devices Input Buffer Primitive */
module fiftyfivenm_io_ibuf
(output o, input i, input ibar);
assign ibar = ibar;
assign o = i;
endmodule // fiftyfivenm_io_ibuf
/* Altera MAX10 devices Output Buffer Primitive */
module fiftyfivenm_io_obuf
(output o, input i, input oe);
assign o = i;
assign oe = oe;
endmodule // fiftyfivenm_io_obuf
/* Altera MAX10 4-input non-fracturable LUT Primitive */
module fiftyfivenm_lcell_comb
(output combout, cout,
input dataa, datab, datac, datad, cin);
/* Internal parameters which define the behaviour
of the LUT primitive.
lut_mask define the lut function, can be expressed in 16-digit bin or hex.
sum_lutc_input define the type of LUT (combinational | arithmetic).
dont_touch for retiming || carry options.
lpm_type for WYSIWYG */
parameter lut_mask = 16'hFFFF;
parameter dont_touch = "off";
parameter lpm_type = "fiftyfivenm_lcell_comb";
parameter sum_lutc_input = "datac";
reg [1:0] lut_type;
reg cout_rt;
reg combout_rt;
wire dataa_w;
wire datab_w;
wire datac_w;
wire datad_w;
wire cin_w;
assign dataa_w = dataa;
assign datab_w = datab;
assign datac_w = datac;
assign datad_w = datad;
function lut_data;
input [15:0] mask;
input dataa, datab, datac, datad;
reg [7:0] s3;
reg [3:0] s2;
reg [1:0] s1;
begin
s3 = datad ? mask[15:8] : mask[7:0];
s2 = datac ? s3[7:4] : s3[3:0];
s1 = datab ? s2[3:2] : s2[1:0];
lut_data = dataa ? s1[1] : s1[0];
end
endfunction
initial begin
if (sum_lutc_input == "datac") lut_type = 0;
else
if (sum_lutc_input == "cin") lut_type = 1;
else begin
$error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input);
$finish();
end
end
always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
if (lut_type == 0) begin // logic function
combout_rt = lut_data(lut_mask, dataa_w, datab_w,
datac_w, datad_w);
end
else if (lut_type == 1) begin // arithmetic function
combout_rt = lut_data(lut_mask, dataa_w, datab_w,
cin_w, datad_w);
end
cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0);
end
assign combout = combout_rt & 1'b1;
assign cout = cout_rt & 1'b1;
endmodule // fiftyfivenm_lcell_comb
/* Altera D Flip-Flop Primitive */
module dffeas
(output q,
input d, clk, clrn, prn, ena,
input asdata, aload, sclr, sload);
// Timing simulation is not covered
parameter power_up="dontcare";
parameter is_wysiwyg="false";
reg q_tmp;
wire reset;
reg [7:0] debug_net;
assign reset = (prn && sclr && ~clrn && ena);
assign q = q_tmp & 1'b1;
always @(posedge clk, posedge aload) begin
if(reset) q_tmp <= 0;
else q_tmp <= d;
end
assign q = q_tmp;
endmodule // dffeas
/* MAX10 altpll clearbox model */
(* blackbox *)
module fiftyfivenm_pll
(inclk,
fbin,
fbout,
clkswitch,
areset,
pfdena,
scanclk,
scandata,
scanclkena,
configupdate,
clk,
phasecounterselect,
phaseupdown,
phasestep,
clkbad,
activeclock,
locked,
scandataout,
scandone,
phasedone,
vcooverrange,
vcounderrange);
parameter operation_mode = "normal";
parameter pll_type = "auto";
parameter compensate_clock = "clock0";
parameter inclk0_input_frequency = 0;
parameter inclk1_input_frequency = 0;
parameter self_reset_on_loss_lock = "off";
parameter switch_over_type = "auto";
parameter switch_over_counter = 1;
parameter enable_switch_over_counter = "off";
parameter bandwidth = 0;
parameter bandwidth_type = "auto";
parameter use_dc_coupling = "false";
parameter lock_high = 0;
parameter lock_low = 0;
parameter lock_window_ui = "0.05";
parameter test_bypass_lock_detect = "off";
parameter clk0_output_frequency = 0;
parameter clk0_multiply_by = 0;
parameter clk0_divide_by = 0;
parameter clk0_phase_shift = "0";
parameter clk0_duty_cycle = 50;
parameter clk1_output_frequency = 0;
parameter clk1_multiply_by = 0;
parameter clk1_divide_by = 0;
parameter clk1_phase_shift = "0";
parameter clk1_duty_cycle = 50;
parameter clk2_output_frequency = 0;
parameter clk2_multiply_by = 0;
parameter clk2_divide_by = 0;
parameter clk2_phase_shift = "0";
parameter clk2_duty_cycle = 50;
parameter clk3_output_frequency = 0;
parameter clk3_multiply_by = 0;
parameter clk3_divide_by = 0;
parameter clk3_phase_shift = "0";
parameter clk3_duty_cycle = 50;
parameter clk4_output_frequency = 0;
parameter clk4_multiply_by = 0;
parameter clk4_divide_by = 0;
parameter clk4_phase_shift = "0";
parameter clk4_duty_cycle = 50;
parameter pfd_min = 0;
parameter pfd_max = 0;
parameter vco_min = 0;
parameter vco_max = 0;
parameter vco_center = 0;
// Advanced user parameters
parameter m_initial = 1;
parameter m = 0;
parameter n = 1;
parameter c0_high = 1;
parameter c0_low = 1;
parameter c0_initial = 1;
parameter c0_mode = "bypass";
parameter c0_ph = 0;
parameter c1_high = 1;
parameter c1_low = 1;
parameter c1_initial = 1;
parameter c1_mode = "bypass";
parameter c1_ph = 0;
parameter c2_high = 1;
parameter c2_low = 1;
parameter c2_initial = 1;
parameter c2_mode = "bypass";
parameter c2_ph = 0;
parameter c3_high = 1;
parameter c3_low = 1;
parameter c3_initial = 1;
parameter c3_mode = "bypass";
parameter c3_ph = 0;
parameter c4_high = 1;
parameter c4_low = 1;
parameter c4_initial = 1;
parameter c4_mode = "bypass";
parameter c4_ph = 0;
parameter m_ph = 0;
parameter clk0_counter = "unused";
parameter clk1_counter = "unused";
parameter clk2_counter = "unused";
parameter clk3_counter = "unused";
parameter clk4_counter = "unused";
parameter c1_use_casc_in = "off";
parameter c2_use_casc_in = "off";
parameter c3_use_casc_in = "off";
parameter c4_use_casc_in = "off";
parameter m_test_source = -1;
parameter c0_test_source = -1;
parameter c1_test_source = -1;
parameter c2_test_source = -1;
parameter c3_test_source = -1;
parameter c4_test_source = -1;
parameter vco_multiply_by = 0;
parameter vco_divide_by = 0;
parameter vco_post_scale = 1;
parameter vco_frequency_control = "auto";
parameter vco_phase_shift_step = 0;
parameter charge_pump_current = 10;
parameter loop_filter_r = "1.0";
parameter loop_filter_c = 0;
parameter pll_compensation_delay = 0;
parameter lpm_type = "fiftyfivenm_pll";
parameter phase_counter_select_width = 3;
input [1:0] inclk;
input fbin;
input clkswitch;
input areset;
input pfdena;
input [phase_counter_select_width - 1:0] phasecounterselect;
input phaseupdown;
input phasestep;
input scanclk;
input scanclkena;
input scandata;
input configupdate;
output [4:0] clk;
output [1:0] clkbad;
output activeclock;
output locked;
output scandataout;
output scandone;
output fbout;
output phasedone;
output vcooverrange;
output vcounderrange;
endmodule // cycloneive_pll

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/register.h"
#include "kernel/celltypes.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct SynthIntelPass : public ScriptPass {
SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") { }
virtual void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" synth_intel [options]\n");
log("\n");
log("This command runs synthesis for Intel FPGAs.\n");
log("\n");
log(" -family < max10 | a10gx | cyclonev | cycloneiv | cycloneive>\n");
log(" generate the synthesis netlist for the specified family.\n");
log(" MAX10 is the default target if not family argument specified.\n");
log(" For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n");
log(" Cyclone V and Arria 10 GX devices are experimental, use it with a10gx argument.\n");
log("\n");
log(" -top <module>\n");
log(" use the specified module as top module (default='top')\n");
log("\n");
log(" -vqm <file>\n");
log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n");
log(" output file is omitted if this parameter is not specified.\n");
log("\n");
log(" -run <from_label>:<to_label>\n");
log(" only run the commands between the labels (see below). an empty\n");
log(" from label is synonymous to 'begin', and empty to label is\n");
log(" synonymous to the end of the command list.\n");
log("\n");
log(" -nobram\n");
log(" do not use altsyncram cells in output netlist\n");
log("\n");
log(" -noflatten\n");
log(" do not flatten design before synthesis\n");
log("\n");
log(" -retime\n");
log(" run 'abc' with -dff option\n");
log("\n");
log(" -nobasenradix\n");
log(" dump the VQM netlist in clearbox format for certain defparam primitives\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
log("\n");
}
string top_opt, family_opt, vout_file;
bool retime, flatten, nobram;
virtual void clear_flags() YS_OVERRIDE
{
top_opt = "-auto-top";
family_opt = "max10";
vout_file = "";
retime = false;
flatten = true;
nobram = false;
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
string run_from, run_to;
clear_flags();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-family" && argidx+1 < args.size()) {
family_opt = args[++argidx];
continue;
}
if (args[argidx] == "-top" && argidx+1 < args.size()) {
top_opt = "-top " + args[++argidx];
continue;
}
if (args[argidx] == "-vqm" && argidx+1 < args.size()) {
vout_file = args[++argidx];
continue;
}
if (args[argidx] == "-run" && argidx+1 < args.size()) {
size_t pos = args[argidx+1].find(':');
if (pos == std::string::npos)
break;
run_from = args[++argidx].substr(0, pos);
run_to = args[argidx].substr(pos+1);
continue;
}
if (args[argidx] == "-nobram") {
nobram = true;
continue;
}
if (args[argidx] == "-flatten") {
flatten = true;
continue;
}
if (args[argidx] == "-retime") {
retime = true;
continue;
}
break;
}
extra_args(args, argidx, design);
if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n");
if (family_opt != "max10" && family_opt !="a10gx" && family_opt != "cyclonev" && family_opt !="cycloneiv" && family_opt !="cycloneive")
log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
log_header(design, "Executing SYNTH_INTEL pass.\n");
log_push();
run_script(design, run_from, run_to);
log_pop();
}
virtual void script() YS_OVERRIDE
{
if (check_label("begin"))
{
if(check_label("family") && family_opt=="max10")
run("read_verilog -sv -lib +/intel/max10/cells_sim.v");
else if(check_label("family") && family_opt=="a10gx")
run("read_verilog -sv -lib +/intel/a10gx/cells_sim.v");
else if(check_label("family") && family_opt=="cyclonev")
run("read_verilog -sv -lib +/intel/cyclonev/cells_sim.v");
else if(check_label("family") && family_opt=="cycloneiv")
run("read_verilog -sv -lib +/intel/cycloneiv/cells_sim.v");
else
run("read_verilog -sv -lib +/intel/cycloneive/cells_sim.v");
// Misc and common cells
run("read_verilog -sv -lib +/intel/common/m9k_bb.v");
run("read_verilog -sv -lib +/intel/common/altpll_bb.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
}
if (flatten && check_label("flatten", "(unless -noflatten)"))
{
run("proc");
run("flatten");
run("tribuf -logic");
run("deminout");
}
if (check_label("coarse"))
{
run("synth -run coarse");
}
if (!nobram && check_label("bram", "(skip if -nobram)"))
{
run("memory_bram -rules +/intel/common/brams.txt");
run("techmap -map +/intel/common/brams_map.v");
}
if (check_label("fine"))
{
run("opt -fast -mux_undef -undriven -fine -full");
run("memory_map");
run("opt -undriven -fine");
run("dffsr2dff");
run("dff2dffe -direct-match $_DFF_*");
run("opt -fine");
run("techmap -map +/techmap.v");
run("opt -full");
run("clean -purge");
run("setundef -undriven -zero");
if (retime || help_mode)
run("abc -markgroups -dff", "(only if -retime)");
}
if (check_label("map_luts"))
{
if(family_opt=="a10gx" || family_opt=="cyclonev")
run("abc -luts 2:2,3,6:5,10" + string(retime ? " -dff" : ""));
else
run("abc -lut 4" + string(retime ? " -dff" : ""));
run("clean");
}
if (check_label("map_cells"))
{
run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I");
if(family_opt=="max10")
run("techmap -map +/intel/max10/cells_map.v");
else if(family_opt=="a10gx")
run("techmap -map +/intel/a10gx/cells_map.v");
else if(family_opt=="cyclonev")
run("techmap -map +/intel/cyclonev/cells_map.v");
else if(family_opt=="cycloneiv")
run("techmap -map +/intel/cycloneiv/cells_map.v");
else
run("techmap -map +/intel/cycloneive/cells_map.v");
run("dffinit -ff dffeas Q INIT");
run("clean -purge");
}
if (check_label("check"))
{
run("hierarchy -check");
run("stat");
run("check -noinit");
}
if (check_label("vqm"))
{
if (!vout_file.empty() || help_mode)
run(stringf("write_verilog -attr2comment -defparam -nohex -nobasenradix -renameprefix syn_ %s",
help_mode ? "<file-name>" : vout_file.c_str()));
}
}
} SynthIntelPass;
PRIVATE_NAMESPACE_END