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Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now
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31 changed files with 2969 additions and 729 deletions
65
techlibs/achronix/speedster22i/cells_arith_speedster.v
Executable file
65
techlibs/achronix/speedster22i/cells_arith_speedster.v
Executable file
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// NOTE: This is still WIP.
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(* techmap_celltype = "$alu" *)
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module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] X, Y;
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input CI, BI;
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//output [Y_WIDTH-1:0] CO;
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output CO;
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wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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wire [Y_WIDTH-1:0] AA = A_buf;
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wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
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//wire [Y_WIDTH:0] C = {CO, CI};
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wire [Y_WIDTH+1:0] COx;
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wire [Y_WIDTH+1:0] C = {COx, CI};
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/* Start implementation */
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(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
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genvar i;
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generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
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if(i==Y_WIDTH-1) begin
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(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH]));
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assign CO = COx[Y_WIDTH];
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end
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else
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fiftyfivenm_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1]));
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end: slice
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endgenerate
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/* End implementation */
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assign X = AA ^ BB;
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endmodule
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127
techlibs/achronix/speedster22i/cells_comb_speedster.v
Executable file
127
techlibs/achronix/speedster22i/cells_comb_speedster.v
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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module VCC (output V);
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assign V = 1'b1;
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endmodule // VCC
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module GND (output G);
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assign G = 1'b0;
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endmodule // GND
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/* Altera MAX10 devices Input Buffer Primitive */
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module PADIN (output padout, input padin);
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assign padout = padin;
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endmodule // fiftyfivenm_io_ibuf
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/* Altera MAX10 devices Output Buffer Primitive */
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module PADOUT (output padout, input padin, input oe);
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assign padout = padin;
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assign oe = oe;
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endmodule // fiftyfivenm_io_obuf
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/* Altera MAX10 4-input non-fracturable LUT Primitive */
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module LUT4 (output dout,
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input din0, din1, din2, din3);
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/* Internal parameters which define the behaviour
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of the LUT primitive.
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lut_mask define the lut function, can be expressed in 16-digit bin or hex.
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sum_lutc_input define the type of LUT (combinational | arithmetic).
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dont_touch for retiming || carry options.
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lpm_type for WYSIWYG */
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parameter lut_function = 16'hFFFF;
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//parameter dont_touch = "off";
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//parameter lpm_type = "fiftyfivenm_lcell_comb";
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//parameter sum_lutc_input = "datac";
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reg [1:0] lut_type;
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reg cout_rt;
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reg combout_rt;
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wire dataa_w;
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wire datab_w;
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wire datac_w;
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wire datad_w;
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wire cin_w;
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assign dataa_w = din0;
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assign datab_w = din1;
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assign datac_w = din2;
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assign datad_w = din3;
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function lut_data;
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input [15:0] mask;
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input dataa, datab, datac, datad;
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reg [7:0] s3;
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reg [3:0] s2;
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reg [1:0] s1;
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begin
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s3 = datad ? mask[15:8] : mask[7:0];
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s2 = datac ? s3[7:4] : s3[3:0];
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s1 = datab ? s2[3:2] : s2[1:0];
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lut_data = dataa ? s1[1] : s1[0];
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end
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endfunction
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initial begin
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/*if (sum_lutc_input == "datac")*/ lut_type = 0;
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/*else
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if (sum_lutc_input == "cin") lut_type = 1;
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else begin
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$error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input);
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$finish();
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end*/
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end
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always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
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if (lut_type == 0) begin // logic function
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combout_rt = lut_data(lut_function, dataa_w, datab_w,
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datac_w, datad_w);
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end
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else if (lut_type == 1) begin // arithmetic function
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combout_rt = lut_data(lut_function, dataa_w, datab_w,
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cin_w, datad_w);
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end
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cout_rt = lut_data(lut_function, dataa_w, datab_w, cin_w, 'b0);
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end
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assign dout = combout_rt & 1'b1;
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//assign cout = cout_rt & 1'b1;
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endmodule // fiftyfivenm_lcell_comb
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/* Altera MAX10 D Flip-Flop Primitive */
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// TODO: Implement advanced simulation functions
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module dffeas ( output q,
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input d, clk, clrn, prn, ena,
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input asdata, aload, sclr, sload );
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parameter power_up="dontcare";
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parameter is_wysiwyg="false";
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reg q;
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always @(posedge clk)
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q <= d;
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endmodule
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88
techlibs/achronix/speedster22i/cells_map_speedster.v
Executable file
88
techlibs/achronix/speedster22i/cells_map_speedster.v
Executable file
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@ -0,0 +1,88 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// Normal mode DFF negedge clk, negedge reset
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module \$_DFF_N_ (input D, C, output Q);
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parameter WYSIWYG="TRUE";
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dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
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endmodule
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// Normal mode DFF
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module \$_DFF_P_ (input D, C, output Q);
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parameter WYSIWYG="TRUE";
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dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
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endmodule
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// Async Active Low Reset DFF
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module \$_DFF_PN0_ (input D, C, R, output Q);
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parameter WYSIWYG="TRUE";
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dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
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endmodule
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// Async Active High Reset DFF
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module \$_DFF_PP0_ (input D, C, R, output Q);
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parameter WYSIWYG="TRUE";
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wire R_i = ~ R;
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dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
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endmodule
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// Async Active Low Reset DFF
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module \$_DFF_PN0_ (input D, C, R, output Q);
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parameter WYSIWYG="TRUE";
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dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
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endmodule
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/* */
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module \$__DFFE_PP0 (input D, C, E, R, output Q);
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parameter WYSIWYG="TRUE";
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wire E_i = ~ E;
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dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
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endmodule
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// Input buffer map
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module \$__inpad (input I, output O);
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PADIN _TECHMAP_REPLACE_ (.padout(O), .padin(I));
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endmodule
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// Output buffer map
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module \$__outpad (input I, output O);
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PADOUT _TECHMAP_REPLACE_ (.padout(O), .padin(I), .oe(1'b1));
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endmodule
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// LUT Map
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/* 0 -> datac
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1 -> cin */
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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input [WIDTH-1:0] A;
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output Y;
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generate
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if (WIDTH == 1) begin
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assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
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end else
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if (WIDTH == 2) begin
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LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0),.din3(1'b0));
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end else
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if(WIDTH == 3) begin
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LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]),.din3(1'b0));
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end else
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if(WIDTH == 4) begin
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LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3]));
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end else
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wire _TECHMAP_FAIL_ = 1;
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endgenerate
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endmodule //
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