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	Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now
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					 31 changed files with 2969 additions and 729 deletions
				
			
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			@ -33,7 +33,7 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, defparam;
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bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, defparam, nobasenradix;
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int auto_name_counter, auto_name_offset, auto_name_digits;
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std::map<RTLIL::IdString, int> auto_name_map;
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std::set<RTLIL::IdString> reg_wires, reg_ct;
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			@ -174,8 +174,12 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
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			}
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			if (set_signed && val < 0)
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				f << stringf("-32'sd%u", -val);
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			else
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				f << stringf("32'%sd%u", set_signed ? "s" : "", val);
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			else {
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                                if(!nobasenradix)
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                                  f << stringf("%u", val); // There's no signed parameter on megawizard IP 
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                                else
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                                       f << stringf("32'%sd%u", set_signed ? "s" : "", val);
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                       }
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		} else {
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	dump_hex:
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			if (nohex)
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			@ -1485,6 +1489,10 @@ struct VerilogBackend : public Backend {
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		log("    -v\n");
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		log("        verbose output (print new names of all renamed wires and cells)\n");
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		log("\n");
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		log("    -nobasenradix\n");
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		log("        dump defparam constants without size and radix for align with legacy\n");
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		log("        MegaWizard primitive template implementation.\n");
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		log("\n");
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		log("Note that RTLIL processes can't always be mapped directly to Verilog\n");
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		log("always blocks. This frontend should only be used to export an RTLIL\n");
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		log("netlist, i.e. after the \"proc\" pass has been used to convert all\n");
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			@ -1505,6 +1513,7 @@ struct VerilogBackend : public Backend {
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		nohex = false;
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		nostr = false;
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		defparam = false;
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                nobasenradix= false;
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		auto_prefix = "";
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		bool blackboxes = false;
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			@ -1575,6 +1584,10 @@ struct VerilogBackend : public Backend {
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				defparam = true;
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				continue;
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			}
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                        if (arg == "-nobasenradix") {
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                          defparam = true;
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                          continue;
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			}
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			if (arg == "-blackboxes") {
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				blackboxes = true;
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				continue;
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