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Make keep_cache_t process all modules up-front instead of on-demand
We will want to query `keep_cache` from parallel threads. If we compute the results on-demand, that means we need synchronization for cache access in those queries, which adds complexity and overhead. Instead, prefill the cache with the status of all relevant modules. Note that this doesn't actually do more work --- we always consult `keep_cache` for all cells of all selected modules, so scanning all those cells and determining the kept status of all dependency modules is always required. Later in this PR we're going to parallelize `scan_module` itself, and that's also much easier to do when no other parallel threads are running.
This commit is contained in:
Robert O'Callahan
parent
c8298aae02
commit
cba49642aa
1 changed files with 103 additions and 59 deletions
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@ -33,47 +33,95 @@ using RTLIL::id2cstr;
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struct keep_cache_t
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{
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Design *design;
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dict<Module*, bool> cache;
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bool purge_mode = false;
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dict<Module*, bool> keep_modules;
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bool purge_mode;
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void reset(Design *design = nullptr, bool purge_mode = false)
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{
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this->design = design;
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this->purge_mode = purge_mode;
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cache.clear();
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}
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bool query(Module *module)
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{
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log_assert(design != nullptr);
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if (module == nullptr)
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return false;
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if (cache.count(module))
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return cache.at(module);
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cache[module] = true;
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if (!module->get_bool_attribute(ID::keep)) {
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bool found_keep = false;
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for (auto cell : module->cells())
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if (query(cell, true /* ignore_specify */)) {
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found_keep = true;
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break;
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}
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for (auto wire : module->wires())
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if (wire->get_bool_attribute(ID::keep)) {
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found_keep = true;
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break;
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}
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cache[module] = found_keep;
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keep_cache_t(bool purge_mode, const std::vector<RTLIL::Module *> &selected_modules)
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: purge_mode(purge_mode) {
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std::vector<RTLIL::Module *> scan_modules_worklist;
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dict<RTLIL::Module *, std::vector<RTLIL::Module*>> dependents;
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std::vector<RTLIL::Module *> propagate_kept_modules_worklist;
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for (RTLIL::Module *module : selected_modules) {
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if (keep_modules.count(module))
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continue;
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bool keep = scan_module(module, dependents, true, scan_modules_worklist);
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keep_modules[module] = keep;
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if (keep)
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propagate_kept_modules_worklist.push_back(module);
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}
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return cache[module];
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while (!scan_modules_worklist.empty()) {
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RTLIL::Module *module = scan_modules_worklist.back();
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scan_modules_worklist.pop_back();
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if (keep_modules.count(module))
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continue;
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bool keep = scan_module(module, dependents, false, scan_modules_worklist);
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keep_modules[module] = keep;
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if (keep)
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propagate_kept_modules_worklist.push_back(module);
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}
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while (!propagate_kept_modules_worklist.empty()) {
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RTLIL::Module *module = propagate_kept_modules_worklist.back();
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propagate_kept_modules_worklist.pop_back();
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for (RTLIL::Module *dependent : dependents[module]) {
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if (keep_modules[dependent])
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continue;
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keep_modules[dependent] = true;
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propagate_kept_modules_worklist.push_back(dependent);
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}
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}
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}
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bool query(Cell *cell, bool ignore_specify = false)
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bool query(Cell *cell) const
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{
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if (keep_cell(cell, purge_mode))
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return true;
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if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
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return true;
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if (cell->module && cell->module->design) {
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RTLIL::Module *cell_module = cell->module->design->module(cell->type);
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return cell_module != nullptr && keep_modules.at(cell_module);
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}
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return false;
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}
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private:
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bool scan_module(Module *module, dict<RTLIL::Module *, std::vector<RTLIL::Module*>> &dependents,
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bool scan_all_cells, std::vector<Module*> &worklist) const
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{
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bool keep = false;
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if (module->get_bool_attribute(ID::keep)) {
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if (!scan_all_cells)
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return true;
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keep = true;
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}
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for (Cell *cell : module->cells()) {
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if (keep_cell(cell, purge_mode)) {
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if (!scan_all_cells)
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return true;
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keep = true;
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}
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if (module->design) {
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RTLIL::Module *cell_module = module->design->module(cell->type);
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if (cell_module != nullptr) {
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dependents[cell_module].push_back(module);
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worklist.push_back(cell_module);
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}
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}
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}
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if (!scan_all_cells && keep)
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return true;
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for (Wire *wire : module->wires()) {
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if (wire->get_bool_attribute(ID::keep)) {
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return true;
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}
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}
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return keep;
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}
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static bool keep_cell(Cell *cell, bool purge_mode)
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{
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if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
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return true;
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@ -81,9 +129,6 @@ struct keep_cache_t
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if (cell->type.in(ID($overwrite_tag)))
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return true;
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if (!ignore_specify && cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
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return true;
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if (cell->type == ID($print) || cell->type == ID($check))
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return true;
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@ -92,19 +137,14 @@ struct keep_cache_t
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if (!purge_mode && cell->type == ID($scopeinfo))
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return true;
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if (cell->module && cell->module->design)
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return query(cell->module->design->module(cell->type));
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return false;
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}
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};
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keep_cache_t keep_cache;
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CellTypes ct_reg, ct_all;
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int count_rm_cells, count_rm_wires;
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void rmunused_module_cells(Module *module, bool verbose)
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void rmunused_module_cells(Module *module, bool verbose, keep_cache_t &keep_cache)
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{
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SigMap sigmap(module);
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dict<IdString, pool<Cell*>> mem2cells;
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@ -595,7 +635,7 @@ bool rmunused_module_init(RTLIL::Module *module, bool verbose)
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return did_something;
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}
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void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool rminit)
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void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool rminit, keep_cache_t &keep_cache)
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{
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if (verbose)
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log("Finding unused cells or wires in module %s..\n", module->name);
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@ -652,7 +692,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool
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if (!delcells.empty())
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module->design->scratchpad_set_bool("opt.did_something", true);
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rmunused_module_cells(module, verbose);
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rmunused_module_cells(module, verbose, keep_cache);
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while (rmunused_module_signals(module, purge_mode, verbose)) { }
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if (rminit && rmunused_module_init(module, verbose))
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@ -695,7 +735,12 @@ struct OptCleanPass : public Pass {
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}
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extra_args(args, argidx, design);
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keep_cache.reset(design, purge_mode);
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std::vector<RTLIL::Module*> selected_modules;
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for (auto module : design->selected_whole_modules_warn()) {
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if (!module->has_processes_warn())
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selected_modules.push_back(module);
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}
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keep_cache_t keep_cache(purge_mode, selected_modules);
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ct_reg.setup_internals_mem();
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ct_reg.setup_internals_anyinit();
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@ -706,10 +751,8 @@ struct OptCleanPass : public Pass {
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count_rm_cells = 0;
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count_rm_wires = 0;
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for (auto module : design->selected_whole_modules_warn()) {
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if (module->has_processes_warn())
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continue;
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rmunused_module(module, purge_mode, true, true);
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for (auto module : selected_modules) {
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rmunused_module(module, purge_mode, true, true, keep_cache);
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}
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if (count_rm_cells > 0 || count_rm_wires > 0)
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@ -718,7 +761,6 @@ struct OptCleanPass : public Pass {
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design->optimize();
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design->check();
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keep_cache.reset();
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ct_reg.clear();
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ct_all.clear();
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log_pop();
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@ -758,7 +800,12 @@ struct CleanPass : public Pass {
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}
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extra_args(args, argidx, design);
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keep_cache.reset(design);
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std::vector<RTLIL::Module*> selected_modules;
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for (auto module : design->selected_unboxed_whole_modules()) {
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if (!module->has_processes())
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selected_modules.push_back(module);
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}
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keep_cache_t keep_cache(purge_mode, selected_modules);
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ct_reg.setup_internals_mem();
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ct_reg.setup_internals_anyinit();
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@ -769,10 +816,8 @@ struct CleanPass : public Pass {
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count_rm_cells = 0;
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count_rm_wires = 0;
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for (auto module : design->selected_unboxed_whole_modules()) {
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if (module->has_processes())
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continue;
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rmunused_module(module, purge_mode, ys_debug(), true);
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for (auto module : selected_modules) {
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rmunused_module(module, purge_mode, ys_debug(), true, keep_cache);
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}
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log_suppressed();
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@ -782,7 +827,6 @@ struct CleanPass : public Pass {
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design->optimize();
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design->check();
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keep_cache.reset();
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ct_reg.clear();
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ct_all.clear();
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