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verilog: disallow overriding global parameters

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It was previously possible to override global parameters on a
per-instance basis. This could be dangerous when using positional
parameter bindings, hiding oversupplied parameters.
This commit is contained in:
Zachary Snow 2021-03-11 11:49:15 -05:00
parent 83fc5cc28b
commit cb9f3b6abf
2 changed files with 18 additions and 0 deletions
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2
frontends/ast/ast.cc
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@ -1286,6 +1286,8 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
}
else {
// must be global definition
if ((*it)->type == AST_PARAMETER)
(*it)->type = AST_LOCALPARAM; // cannot be overridden
(*it)->simplify(false, false, false, 1, -1, false, false); //process enum/other declarations
design->verilog_globals.push_back((*it)->clone());
current_scope.clear();