3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 06:03:23 +00:00

Improvements in assertpmux

This commit is contained in:
Clifford Wolf 2016-09-07 12:42:16 +02:00
parent e2570ffb87
commit cb7dbf4070
6 changed files with 202 additions and 23 deletions

View file

@ -1975,6 +1975,22 @@ RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec
return cell;
}
RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width)
{
RTLIL::SigSpec sig = addWire(NEW_ID, width);
Cell *cell = addCell(name, "$anyconst");
cell->setParam("\\WIDTH", width);
cell->setPort("\\Y", sig);
return sig;
}
RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name)
{
RTLIL::SigSpec sig = addWire(NEW_ID);
Cell *cell = addCell(name, "$initstate");
cell->setPort("\\Y", sig);
return sig;
}
RTLIL::Wire::Wire()
{