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	Fixed sharing of reduce operator
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					 1 changed files with 13 additions and 0 deletions
				
			
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					@ -252,6 +252,19 @@ struct ShareWorker
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		if (config.generic_uni_ops.count(c1->type))
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							if (config.generic_uni_ops.count(c1->type))
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		{
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							{
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								if (c1->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool") && c1->getParam("\\A_WIDTH").as_int() != c2->getParam("\\A_WIDTH").as_int())
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								{
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									RTLIL::SigBit extbit = c1->type == "$reduce_and" ? RTLIL::State::S1 : RTLIL::State::S0;
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									while (c1->getParam("\\A_WIDTH").as_int() < c2->getParam("\\A_WIDTH").as_int()) {
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										c1->setParam("\\A_WIDTH", c1->getParam("\\A_WIDTH").as_int() + 1);
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										c1->setPort("\\A", {extbit, c1->getPort("\\A")});
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									}
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									while (c2->getParam("\\A_WIDTH").as_int() < c1->getParam("\\A_WIDTH").as_int()) {
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										c2->setParam("\\A_WIDTH", c2->getParam("\\A_WIDTH").as_int() + 1);
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										c2->setPort("\\A", {extbit, c2->getPort("\\A")});
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									}
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								}
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			if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool())
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								if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool())
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			{
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								{
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				RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1;
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									RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1;
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