diff --git a/kernel/register.cc b/kernel/register.cc
index 80a2a5385..c1aa50dd5 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -353,6 +353,7 @@ struct HelpPass : public Pass {
virtual void execute(std::vector<std::string> args, RTLIL::Design*)
{
if (args.size() == 1) {
+ log("\n");
for (auto &it : REGISTER_INTERN::pass_register)
log(" %-20s %s\n", it.first.c_str(), it.second->short_help.c_str());
return;
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index 251d0ba09..ba3494d1d 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -309,7 +309,7 @@ static void handle_loops()
fclose(dot_f);
}
-static void abc_module(RTLIL::Module *current_module, std::string script_file, std::string exe_file, std::string liberty_file, bool cleanup)
+static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, std::string liberty_file, bool cleanup)
{
module = current_module;
map_autoidx = RTLIL::autoidx++;
@@ -328,7 +328,8 @@ static void abc_module(RTLIL::Module *current_module, std::string script_file, s
std::vector<RTLIL::Cell*> cells;
cells.reserve(module->cells.size());
for (auto &it : module->cells)
- cells.push_back(it.second);
+ if (design->selected(current_module, it.second))
+ cells.push_back(it.second);
for (auto c : cells)
extract_cell(c);
@@ -589,7 +590,38 @@ static void abc_module(RTLIL::Module *current_module, std::string script_file, s
}
struct AbcPass : public Pass {
- AbcPass() : Pass("abc") { }
+ AbcPass() : Pass("abc", "use ABC for technology mapping") { }
+ virtual void help()
+ {
+ log("\n");
+ log(" abc [options] [selection]\n");
+ log("\n");
+ log("This pass uses the ABC tool [1] for technology mapping of yosys's internal gate\n");
+ log("library to a target architecture.\n");
+ log("\n");
+ log(" -exe <command>\n");
+ log(" use the specified command name instead of \"abc\" to execute ABC. This\n");
+ log(" can e.g. be used to call a specific version of ABC or a wrapper script.\n");
+ log("\n");
+ log(" -script <file>\n");
+ log(" use the specified ABC script file instead of the default script.\n");
+ log("\n");
+ log(" -liberty <file>\n");
+ log(" generate netlists for the specified cell library (using the liberty\n");
+ log(" file format). This option is ignored if also -script option is also\n");
+ log(" used. Without this option, ABC is used to optimize the netlist but\n");
+ log(" keeps using yosys's internal gate library.\n");
+ log("\n");
+ log(" -nocleanup\n");
+ log(" when this option is used, the tempprary files created be this pass\n");
+ log(" are not removed. this is usefull for debugging.\n");
+ log("\n");
+ log("This pass does not operate on modules with uprocessed processes in it.\n");
+ log("(I.e. the 'proc' pass should be used first to convert processes to netlists.)\n");
+ log("\n");
+ log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
+ log("\n");
+ }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing ABC pass (technology mapping using ABC).\n");
@@ -628,12 +660,13 @@ struct AbcPass : public Pass {
free(pwd);
extra_args(args, argidx, design);
- for (auto &mod_it : design->modules) {
- if (mod_it.second->processes.size() > 0)
- log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str());
- else
- abc_module(mod_it.second, script_file, exe_file, liberty_file, cleanup);
- }
+ for (auto &mod_it : design->modules)
+ if (design->selected(mod_it.second)) {
+ if (mod_it.second->processes.size() > 0)
+ log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str());
+ else
+ abc_module(design, mod_it.second, script_file, exe_file, liberty_file, cleanup);
+ }
assign_map.clear();
signal_list.clear();
diff --git a/passes/dfflibmap/dfflibmap.cc b/passes/dfflibmap/dfflibmap.cc
index 86e8bcbf6..dd873cadd 100644
--- a/passes/dfflibmap/dfflibmap.cc
+++ b/passes/dfflibmap/dfflibmap.cc
@@ -220,13 +220,13 @@ static bool expand_cellmap(std::string pattern, std::string inv)
return return_status;
}
-static void dfflibmap(RTLIL::Module *module)
+static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
{
log("Mapping DFF cells in module `%s':\n", module->name.c_str());
std::vector<RTLIL::Cell*> cell_list;
for (auto &it : module->cells) {
- if (cell_mappings.count(it.second->type) > 0)
+ if (design->selected(module, it.second) && cell_mappings.count(it.second->type) > 0)
cell_list.push_back(it.second);
}
@@ -266,7 +266,19 @@ static void dfflibmap(RTLIL::Module *module)
}
struct DfflibmapPass : public Pass {
- DfflibmapPass() : Pass("dfflibmap") { }
+ DfflibmapPass() : Pass("dfflibmap", "technology mapping of flip-flops") { }
+ virtual void help()
+ {
+ log("\n");
+ log(" dfflibmap -liberty <file> [selection]\n");
+ log("\n");
+ log("Map internal flip-flop cells to the flip-flop cells in the technology\n");
+ log("library specified in the given liberty file.\n");
+ log("\n");
+ log("This pass may add inverters as needed. Therefore it is recommended to\n");
+ log("first run this pass and then map the logic paths to the target technology.\n");
+ log("\n");
+ }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n");
@@ -318,7 +330,8 @@ struct DfflibmapPass : public Pass {
logmap_all();
for (auto &it : design->modules)
- dfflibmap(it.second);
+ if (design->selected(it.second))
+ dfflibmap(design, it.second);
cell_mappings.clear();
}
diff --git a/passes/extract/extract.cc b/passes/extract/extract.cc
index 1907ef5ed..eab1a1693 100644
--- a/passes/extract/extract.cc
+++ b/passes/extract/extract.cc
@@ -44,8 +44,8 @@ namespace
return false;
}
- if (mod->memories.size() > 0 || mod->processes.size() > 0) {
- log(" Skipping module %s as it contains unprocessed memories or processes.\n", mod->name.c_str());
+ if (mod->processes.size() > 0) {
+ log(" Skipping module %s as it contains unprocessed processes.\n", mod->name.c_str());
return false;
}
@@ -203,7 +203,52 @@ namespace
}
struct ExtractPass : public Pass {
- ExtractPass() : Pass("extract") { }
+ ExtractPass() : Pass("extract", "find subcircuits and replace them with cells") { }
+ virtual void help()
+ {
+ log("\n");
+ log(" extract -map <map_file> [options] [selection]\n");
+ log("\n");
+ log("This pass looks for subcircuits that are isomorphic to any of the modules\n");
+ log("in the given map file and replaces them with instances of this modules. The\n");
+ log("map file can be a verilog source file (*.v) or an ilang file (*.il).\n");
+ log("\n");
+ log(" -map <map_file>\n");
+ log(" use the modules in this file as reference\n");
+ log("\n");
+ log(" -verbose\n");
+ log(" print debug output while analyzing\n");
+ log("\n");
+ log(" -constports\n");
+ log(" also find instances with constant drivers. this may be much\n");
+ log(" slower than the normal operation.\n");
+ log("\n");
+ log(" -nodefaultswaps\n");
+ log(" normally builtin port swapping rules for internal cells are used per\n");
+ log(" default. This turns that off, so e.g. 'a^b' does not match 'b^a'\n");
+ log(" when this option is used.\n");
+ log("\n");
+ log(" -compat <needle_type> <haystack_type>\n");
+ log(" Per default, the cells in the map file (needle) must have the\n");
+ log(" type as the cells in the active design (haystack). This option\n");
+ log(" can be used to register additional pairs of types that should\n");
+ log(" match. This option can be used multiple times.\n");
+ log("\n");
+ log(" -swap <needle_type> <port1>,<port2>[,...]\n");
+ log(" Register a set of swapable ports for a needle cell type.\n");
+ log(" This option can be used multiple times.\n");
+ log("\n");
+ log(" -perm <needle_type> <port1>,<port2>[,...] <portA>,<portB>[,...]\n");
+ log(" Register a valid permutation of swapable ports for a needle\n");
+ log(" cell type. This option can be used multiple times.\n");
+ log("\n");
+ log("This pass does not operate on modules with uprocessed processes in it.\n");
+ log("(I.e. the 'proc' pass should be used first to convert processes to netlists.)\n");
+ log("\n");
+ log("This pass operates on whole modules or selected cells from modules. Other\n");
+ log("selected entities (wires, etc.) are ignored.\n");
+ log("\n");
+ }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing EXTRACT pass (map subcircuits to cells).\n");