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write_verilog: only warn on processes with sync rules.

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Processes without sync rules correspond to simple decision trees that
directly correspond to `always @*` or `always_comb` blocks in Verilog,
and do not need a warning.

This removes the need to suppress warnings during the RTLIL-to-Verilog
conversion performed by Amaranth.
This commit is contained in:
Catherine 2024-04-02 11:26:58 +00:00
parent 94170388a9
commit cb07710162
1 changed files with 10 additions and 6 deletions
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16
backends/verilog/verilog_backend.cc
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@ -1070,7 +1070,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf(";\n"); f << stringf(";\n");
return true; return true;
} }
if (cell->type == ID($_BUF_)) { if (cell->type == ID($_BUF_)) {
f << stringf("%s" "assign ", indent.c_str()); f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y)); dump_sigspec(f, cell->getPort(ID::Y));
@ -2276,11 +2276,15 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
active_initdata[sig[i]] = val[i]; active_initdata[sig[i]] = val[i];
} }
if (!module->processes.empty()) bool has_sync_rules = false;
log_warning("Module %s contains unmapped RTLIL processes. RTLIL processes\n" for (auto process : module->processes)
"can't always be mapped directly to Verilog always blocks. Unintended\n" if (!process.second->syncs.empty())
"changes in simulation behavior are possible! Use \"proc\" to convert\n" has_sync_rules = true;
"processes to logic networks and registers.\n", log_id(module)); if (has_sync_rules)
log_warning("Module %s contains RTLIL processes with sync rules. Such RTLIL "
"processes can't always be mapped directly to Verilog always blocks. "
"unintended changes in simulation behavior are possible! Use \"proc\" "
"to convert processes to logic networks and registers.\n", log_id(module));
f << stringf("\n"); f << stringf("\n");
for (auto it = module->processes.begin(); it != module->processes.end(); ++it) for (auto it = module->processes.begin(); it != module->processes.end(); ++it)